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Participant hananz
Participant
1,606 Views
Registered: ‎02-23-2014

pixels per clock

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I'm using to write the HDMI video to my DDR4 memory thru data mover IP. for the simulation of HDMI RX core I use "video timing controller" and "video in to AXI4-stream", on both of them set PPC as 2.

 

On the command of the data mover I need to send the "bytes to transfer" of data that would be delivered thru the data mover, and it seems that when I set it to the amount of the resolution X pixel width [Bytes] there is an error from the data mover, but if I double the "bytes to transfer"  there is no error.

 

it seems that I don't fully understand the PPC since the vtiming_out ("video timing controller") doesn't change and the vid_data width ("video in to AXI4-stream") isn't half of the video out width, then I truly have doubled the data, then why do I need 2 PPC?

 

Thank you,

Hanan 

 

 

 

 

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Moderator
Moderator
1,831 Views
Registered: ‎11-09-2015

Re: pixels per clock

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Hi @hananz,

 

The AXI4-Stream to video out is only using the timing generated from the VTC. It assumes the timing provided is correct (else it won't lock).

 

Then for the VTC, it does not care about pixels-per-clock. You have to provide the correct timing as mentioned in pg016:

VTC.JPG

 

So the tlast timing will change if the hsync timing from the VTC changes. And to have it change, you would need to divide your hsize by 2.

 

Hope that helps,

 

Regards,

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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4 Replies
Moderator
Moderator
1,580 Views
Registered: ‎11-09-2015

Re: pixels per clock

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Hi @hananz,

 

The Video Timing Controller won't change. You are respionsible to configure it properly when changing from 1 to 2 ppc.

 

For the AXI4S to video out or Video in to AXI4S, the data width should change depending if it is set up for 1 or 2 ppc.

 

2ppc can be used to slow the data to use a slower clock and help to meet timing


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
Moderator
1,504 Views
Registered: ‎11-09-2015

Re: pixels per clock

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Hi @hananz,

 

This topic is still open and is waiting for you:

    If your question is answered or your issue is solved, please mark the response which helped as solution
    If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Participant hananz
Participant
1,492 Views
Registered: ‎02-23-2014

Re: pixels per clock

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hi @florentw ,

 

I'm aware to all you have mentioned, but since the total transferred data should stay the same with ppc=1 or ppc=2 or any, I assumed that the AXIS timing (tlast) would be short by x2 (as defined by ppc=2) and it doesn't do that.

 

hanan

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Moderator
Moderator
1,832 Views
Registered: ‎11-09-2015

Re: pixels per clock

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Hi @hananz,

 

The AXI4-Stream to video out is only using the timing generated from the VTC. It assumes the timing provided is correct (else it won't lock).

 

Then for the VTC, it does not care about pixels-per-clock. You have to provide the correct timing as mentioned in pg016:

VTC.JPG

 

So the tlast timing will change if the hsync timing from the VTC changes. And to have it change, you would need to divide your hsize by 2.

 

Hope that helps,

 

Regards,

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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