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Participant krunal_h_bhavsar
Participant
8,202 Views
Registered: ‎09-21-2007

problem in simulation in sysgen 8.2 for HDL netlist and hardware co-simulation

hi,
 
               I want to generate HDL code from system generator and also hardware co-simulation. I have tried it with given system generator's examples. They run properly but don't generate HDL or block for hardware co-simulation.
It gives me the errors given below:
 
"
standard exception: XNetlistEngine:
An exception was raised:
com.xilinx.sysgen.netlist.NetlistInternal: couldn't run c:\Xilinx/bin/nt/coregen -b makeproj at
C:/MATLAB71/toolbox/xilinx/sysgen/scripts/SgGenerateCores.pm line 723.
and sometimes
 
"
standard exception: XNetlistEngine:
An exception was raised:
com.xilinx.sysgen.netlist.NetlistInternal: couldn't make clock wrapper at
C:/MATLAB71/toolbox/xilinx/sysgen/scripts/SgPass2Netlist.pm line 107.
 
"
 
Actually I have generated fixed point MAC and floating point addition and multiplication using Core generator. and in simulation using model sim it works perfactly. I want hardware co-simulation of it. Please help me. I have sparten 3E starter kit with me.
 
Thank you, Please help me.
Regards,
Krunal
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3 Replies
Visitor jacobusn
Visitor
8,200 Views
Registered: ‎08-15-2007

Re: problem in simulation in sysgen 8.2 for HDL netlist and hardware co-simulation

This looks like a problem with you setup. Here's a couple of things you can try.

- Do a clean reinstall of your ISE tools and SysGen + latest IP updates. Make sure not to inlcude spaces in any paths, and also check your Matlab path for spaces
- Check that you have write permissions for the c:\Xilinx/bin/nt/ folder

Jaco
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Participant krunal_h_bhavsar
Participant
8,180 Views
Registered: ‎09-21-2007

Re: problem in simulation in sysgen 8.2 for HDL netlist and hardware co-simulation

Thank you,
           I have installed all software in other PC and it generates Verilog file but it generates many of files so what file I have to use to download in FPGA or for simulation. Please help me.
 
Regards,
Krunal
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Visitor jacobusn
Visitor
8,126 Views
Registered: ‎08-15-2007

Re: problem in simulation in sysgen 8.2 for HDL netlist and hardware co-simulation

You need to be more clear on what you want. What compilation target are you using?

When using Bitstream as your target it will create a XFlow directory which contains all the files from the Xilinx Implementation Flow. In that case you use the .bit file as you would normally do.

When using Hardware Co-Simulation, this directory is also produced, but only for the level of your design where the SysGen token is located (and ofcourse the sublevels of this level). In this case the Hardware Co-Simulation token already points to the correct .bit file location. If you are doing a JTAG HW-Cosim you only need the .bit file when you run the simulation. For other types such as Ethernet it would be different. However if you don't change anything after the token was generated you should not have problems.
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