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Contributor
Contributor
1,113 Views
Registered: ‎05-28-2018

problem in video streaming

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hi, 

i am using spartan 6 fpga, here am using vid_in and vid_out streaming for video streaming application, am not getting syncs and video data output, can any one help me please.

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Contributor
Contributor
965 Views
Registered: ‎05-28-2018

Re: problem in video streaming

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is this a problem related to processing frequency and video frequency mismatch because i gave 100 Mhz for aclk to both the core and 27Mhz for video in clock

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Voyager
Voyager
1,099 Views
Registered: ‎03-28-2016

Re: problem in video streaming

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Unfortunately, there are many things that could be going wrong.  Without more detailed information, I can only give general suggestions.

 

Suggestion number one is to make sure you understand how the Xilinx AXI4-Stream Video IP are expected to operate.  Check out UG934 for an overview.  It's a little dated, but it's still valid.

 

https://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf

 

Suggestion number two is make sure you understand how the Vid_in core is expected to operate.  Check out UG043 for the version of ISE that you are using for detailed information.

 

From your post, it sounds like you are unable to get the vid_in core to lock onto your input video stream.  The very first thing I would suggest is verifying that you have a good input video stream.  If your input video format and your output video format are the same then you could easily build a simple pass-thru design that inputs the video, registers it once on the input, passes it to some output registers and then outputs it.  Another option is to use chipscope to collect samples of the input video stream to verify that you are getting a good input.  Due to limited BRAM in the FPGA, you will not be able to collect an entire frame unless the image size is rather small, but you should be able to collect multiple lines which should be enough to verify the quality of your control signals (HSync, VSync, ...). 

 

After you are confident that you have a good input video stream, you can then start looking at the Vid_In core:

  • Check the reset, vid_io_in_ce and axis_enable signals are correct and not disabling the core
  • Check that the Vid_In is receiving proper input video control signals (active_video, vblank/hblank, vsync/hsync).  Keep in mind that not all of them are required.
  • Check that the Vid_In Axi-Stream output is being properly handled.  In particular make sure that the tready signal is being driven "high".

If any of the above is incorrect, the Vid_In core will not work properly.

 

Finally, here is a link to a set pages on the Video Forum board that provide a nice intro to video processing.

 

https://forums.xilinx.com/t5/Video/Xilinx-Video-Series/td-p/849583

 

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
Contributor
Contributor
1,075 Views
Registered: ‎05-28-2018

Re: problem in video streaming

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ya sure i agree your point, from video in portion am not getting any problem, because i checked in chipscope, where as at video out side signals like locked and first_full_frame were always zero which is giving the output is always low.

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Contributor
Contributor
1,072 Views
Registered: ‎05-28-2018

Re: problem in video streaming

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And i have probed at input section of the video_out core, here am getting video from video_in core, to latch  data out in video_out

controls signals like locked and first_full_frame is always low.   

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Scholar watari
Scholar
1,039 Views
Registered: ‎06-16-2013

Re: problem in video streaming

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Hi @hemanth_93

 

I suggest to refer the following URL, even if the device family is different.

This concept is helpful for you.

Of cause you can learn it by Vivado web edition.

 

https://forums.xilinx.com/t5/Video/Xilinx-Video-Series/td-p/849583

 

I think that this help is suitable for you.

 

Also,  generally, vid_in_axi4s and axi4s_vid_out are requested like video timing generator or ditector.

Because of this logic outputs the video timing for success on AXI4Stream.

 

Best regards,

 

Contributor
Contributor
1,025 Views
Registered: ‎05-28-2018

Re: problem in video streaming

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Hi,

Thanks for replying, 

 

Iteration-I

We have made the connections as shown in Iteration1_toplevel.jpg, but there was no output from video-out core (i.e. all outputs were low). We suspected VDMA block.

 

Iteration-II

To debug further we removed VDMA block and created Iteration-II as shown in Iteration2_toplevel.jpg. We have also added chip scope pro for Iteration-II

 

As seen from chip scope pro, Video-In is passing data and all the timing signals out. It is also generating SOF, EOL properly. But still  there was no output from video-out core (i.e. all outputs were low). 

 

Please suggest the anything missing in the procedure we are following, Thanks. 

 

 

Iteration1_toplevel.jpg
Iteration1_input-VDMA.jpg
Iteration1_VDMA-output.jpg
Iteration1_VDMA-DDR2.jpg
Iteration2_toplevel.jpg
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Scholar watari
Scholar
990 Views
Registered: ‎06-16-2013

Re: problem in video streaming

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Hi @hemanth_93

 

Would you make sure the followings ?

 

- Make sure polarity of reset port in each IPs

- Make sure input floating ports in each IPs

- Make sure output signals on axi4stream to video-out.

=> I guess this IP doesn't lock yet. Make sure it.

 

I have some debug flow for Vivado. But I don't have it for ISE...

 

Best regards,

 

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Contributor
Contributor
966 Views
Registered: ‎05-28-2018

Re: problem in video streaming

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is this a problem related to processing frequency and video frequency mismatch because i gave 100 Mhz for aclk to both the core and 27Mhz for video in clock

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Moderator
Moderator
958 Views
Registered: ‎11-09-2015

Re: problem in video streaming

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Hi @hemanth_93,

 

Thank you for sharing. As you problem is solved could you kindly mark you previous reply as accepted solution to close the topic? Just click on the accept as solution button below your reply while logged in


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**