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Visitor czajak
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Registered: ‎09-10-2017

problem vdma + tpg + vga

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Hello,

I've done project with image processing flow in Vivado 2014.4.

I use Zedboard and want to display image at the screen via VGA and keep it in memory to have opportiunity to read it on the processor.

 

My images are extended and inconsistent. You can see it in the attachments below.

 

I suppose the problem is in the VGA controller. Maybe the timings are not kept properly.

 

In the attachments I add my block design, source code for VGA controller and resulting images.

 

Do you have any idea what is wrong?  

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Moderator
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2,429 Views
Registered: ‎11-09-2015

Re: problem vdma + tpg + vga

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Hi @czajak,

 

I don't understand what you mean saing I don't use VTC's timing signal. Do you think about fsync_out signal? Is it necessary to connect this? I've thought that only vtiming_out interface is nedded.

> The question is why are you using the block vga_0? The AXI4S to video out IP already provide you the data, hsync and vsync signals. So there is no point of using it.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

Re: problem vdma + tpg + vga

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Hi @czajak,

 

Why are you still using 2014.4? I don't think this is the issue but you should consider to move to a newer version (this version is not supported anymore as per Xilinx Support page).

 

Then, in my opinion, it looks like more an synchronization issue with the VDMA than a timing issue.

 

As a first step you should try to connect the TPG directly to the video out IP and see if it works.

 

Hope that helps,

 

Regards,

 

Florent

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor czajak
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Registered: ‎09-10-2017

Re: problem vdma + tpg + vga

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My resulting images are below

 

DSC_2988.JPGDSC_2987.JPGDSC_2986.JPG

 

My block design

block_design.PNG

 

Source code for VGA controller

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity vga is
    Port ( 
		clk25       : in  STD_LOGIC;
		vga_red     : out STD_LOGIC_VECTOR(3 downto 0);
		vga_green   : out STD_LOGIC_VECTOR(3 downto 0);
		vga_blue    : out STD_LOGIC_VECTOR(3 downto 0);
		vga_hsync   : out STD_LOGIC;
		vga_vsync   : out STD_LOGIC;
		frame_pixel : in  STD_LOGIC_VECTOR(23 downto 0)
	 );
end vga;

architecture Behavioral of vga is
   -- Timing constants
   constant hRez       : natural := 640;
   constant hStartSync : natural := 640+16;
   constant hEndSync   : natural := 640+16+96;
   constant hMaxCount  : natural := 800;
	
   constant vRez       : natural := 480;
   constant vStartSync : natural := 480+10;
   constant vEndSync   : natural := 480+10+2;
   constant vMaxCount  : natural := 480+10+2+33;
	
	constant hsync_active : std_logic := '0';
	constant vsync_active : std_logic := '0';

   signal hCounter : unsigned( 9 downto 0) := (others => '0');
   signal vCounter : unsigned( 9 downto 0) := (others => '0');
	signal blank    : std_logic := '1';

begin
	
   process(clk25)
   begin
		if rising_edge(clk25) then
			-- Count the lines and rows      
			if hCounter = hMaxCount-1 then
				hCounter <= (others => '0');
				if vCounter = vMaxCount-1 then
					vCounter <= (others => '0');
				else
					vCounter <= vCounter+1;
				end if;
			else
				hCounter <= hCounter+1;
			end if;

			if blank = '0' then
				vga_red   <= frame_pixel(23 downto 20);
				vga_green <= frame_pixel( 15 downto 12);
				vga_blue  <= frame_pixel( 7 downto 4);
			else
				vga_red   <= (others => '0');
				vga_green <= (others => '0');
				vga_blue  <= (others => '0');
			end if;
			
	
			if vCounter  >= vRez then
				blank <= '1';
			else 
				if hCounter  <640 then
					blank <= '0';
				else
					blank <= '1';
				end if;
			end if;
	
			-- Are we in the hSync pulse? (one has been added to include frame_buffer_latency)
			if hCounter > hStartSync and hCounter <= hEndSync then
				vga_hSync <= hsync_active;
			else
				vga_hSync <= not hsync_active;
			end if;

			-- Are we in the vSync pulse?
			if vCounter >= vStartSync and vCounter <vEndSync then
				vga_vSync <= vsync_active;
			else
				vga_vSync <= not vsync_active;
			end if;
		end if;
	end process;
end Behavioral;
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Registered: ‎11-09-2015

Re: problem vdma + tpg + vga

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Hi @czajak,

 

Also, why using a VTC in your design if you are not using the timing signals from it?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Re: problem vdma + tpg + vga

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Hi @czajak,

 

Any updates on this?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor czajak
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Registered: ‎09-10-2017

Re: problem vdma + tpg + vga

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Hi @florentw,

I use Vivado 2014.4 because in newer version there is TPG done with HLS and I can't configure it.

 

 I connect TPG directly to video out but unfortunatelly it doesn't change anything.

 

I don't understand what you mean saing I don't use VTC's timing signal. Do you think about fsync_out signal? Is it necessary to connect this? I've thought that only vtiming_out interface is nedded.

 

I tried to implement camera module instead of tpg but it doesn't work completely. Only screen with random pixels.

 

Best regards,

 

czajak

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Moderator
Moderator
2,430 Views
Registered: ‎11-09-2015

Re: problem vdma + tpg + vga

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Hi @czajak,

 

I don't understand what you mean saing I don't use VTC's timing signal. Do you think about fsync_out signal? Is it necessary to connect this? I've thought that only vtiming_out interface is nedded.

> The question is why are you using the block vga_0? The AXI4S to video out IP already provide you the data, hsync and vsync signals. So there is no point of using it.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor czajak
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Registered: ‎09-10-2017

Re: problem vdma + tpg + vga

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@florentw 

I tried to change my block design as you said. Below I show it. I only use 12 bits of vid_data, vid_hsync and vid_vsync. 

block_design.PNG But now I have no vga signal. Do you know what could be wrong with this?

My SDK code is below:

    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0x0, 0x4); //reset
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0x0, 0x8); //gen-lock
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0x5C, 0x08000000);
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0x5C+4, 0x0A000000);
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0x5C+8, 0x09000000);
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0x54, 640*3);
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0x58, 0x01002000);
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0x0, 0x83);
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0x50, 480);
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0x30, 0x4); //reset
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0x30, 0x8); //genlock
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0xAC, 0x08000000);
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0xAC+4, 0x0A000000);
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0xAC+8, 0x09000000);
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0xA4, 640*3);
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0xA8, 0x01002000);
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0x30, 0x3);
    XAxiVdma_WriteReg(XPAR_AXI_VDMA_0_BASEADDR, 0xA0, 480);

Best regards,

czajak

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Moderator
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Registered: ‎11-09-2015

Re: problem vdma + tpg + vga

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Hi @czajak,

 

Did you try again with the TPG directly on the AXI4S to video out? Is it working? It should be your first step before using the VDMA

 

The VDMA configuration looks ok, but you can read to the status registers to see if it is flagging any error.

 

Hope that helps,

 

regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor czajak
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Registered: ‎09-10-2017

Re: problem vdma + tpg + vga

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Hi @florentw,

@florentw thank you for your help. It turned out that deleting vga_0 module solved the problem (I didn't see it at first because this was a problem with the vga cable).

 

I got another problem with my project which is a bit different so I post it in a new post. The link is below:

https://forums.xilinx.com/t5/DSP-and-Video/ZYNQ-video-VDMA-problem/td-p/811718

I would be grateful for any comments.

 

Best regards,

czajak

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