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Observer nipunnaina
Observer
1,076 Views
Registered: ‎08-29-2017

refrence clock frequency sources for video phy IP

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I am designing a custom board with Kintex 7 FPGA. I am planning to use Video Phy IP for HDMI transmitter from xilinx. It has input reference clock(mgtrefclk1_pad_p_in, mgtrefclk1_pad_n_in).

I have 2 queries:

 

 

1) I have already an oscillator from 33MHZ on the board for sys_clock. I wanted to use this clock to generate reference clock using FPGA clock resources.In documents it is mentioned, that reference clock should be connected to Input pins. Can I generate it internally?

2)If answer to first query is no, What should be the frequency of external oscillator , which needs to be connected to these pinsmgtrefclk1_pad_p_in, mgtrefclk1_pad_n_in?

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Moderator
Moderator
1,419 Views
Registered: ‎11-09-2015

Re: refrence clock frequency sources for video phy IP

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Hi @nipunnaina,

 

Yes you need an external clock.

 

video PHY ip supports above frequency range with single configuration

Yes it supports all the frequency range with a single HW configuration (in vivado). The VPHY needs to do change using the DRP port but everything should be managed by the driver when you change the video format.

 

You might want to start with the HDMI example design from vivado. Refer to the chap 5 of PG235.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Scholar austin
Scholar
1,063 Views
Registered: ‎02-27-2008

Re: refrence clock frequency sources for video phy IP

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n,

 

Generally, frequencies required tend to be specific to each application, and the standards supported.  Jitter on the clock sources must be very low to meet the standards.  Best is to know what you are doing, and provide fixed crystal oscillator sources as needed.  Supporting multiple standards means either a lot of oscillators, or fewer high quality synthesizers driven by fewer crystals.

 

The internal MMCM and PLL are able to provide simple M/D (fractional integers between 2 and 32) synthesis, but these may have too much jitter for high resolution video, or gigabit transceivers.  Please look at our reference boards for how we provide a few clocks to meet a wide variety of needs.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer nipunnaina
Observer
1,012 Views
Registered: ‎08-29-2017

Re: refrence clock frequency sources for video phy IP

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I have referred UG230 ,page 77. I am planning to use programmable external oscillator. My query is , if I change the frequency in 74MHZ to 297MHZ, do I need to do some changes in video PHY IP configuration(like DRP ports configuration) or video PHY ip supports above frequency range with single configuration.

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Moderator
Moderator
1,420 Views
Registered: ‎11-09-2015

Re: refrence clock frequency sources for video phy IP

Jump to solution

Hi @nipunnaina,

 

Yes you need an external clock.

 

video PHY ip supports above frequency range with single configuration

Yes it supports all the frequency range with a single HW configuration (in vivado). The VPHY needs to do change using the DRP port but everything should be managed by the driver when you change the video format.

 

You might want to start with the HDMI example design from vivado. Refer to the chap 5 of PG235.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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