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Registered: ‎06-13-2013

system generator xps clk mapping problem

Dear Sir,

 

I am using System generator to build a model on Simulink of fall detector application using xilinx blocks, and i am using edk processor to import xps project with microblaze to the model and it succefully implemented on Virtex 5 FPGA. Now i am trying to implement the same model on virtex 6 ML605 evaluation kit, but when comile to generate bitstream i have that error:

 

ERROR:Pack:2908 - The I/O component "xps_clk" has an illegal IOSTANDARD value.
The IOB component is configured to use single-ended signaling and can not use
differential IOSTANDARD value LVDS_25. Two ways to rectify this issue are:
1) Change the IOSTANDARD value to a single-ended standard. 2) Correct the I/O
connectivity by instantiating a differential I/O buffer.

 

part of system.ucf:

Net fpga_0_clk_1_sys_clk_p_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;
Net fpga_0_clk_1_sys_clk_p_pin LOC = J9 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;
Net fpga_0_clk_1_sys_clk_n_pin LOC = H9 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;

 

when i changed IOSTANDARD as follows :

Net fpga_0_clk_1_sys_clk_p_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;
Net fpga_0_clk_1_sys_clk_p_pin LOC = J9 | IOSTANDARD=LVCMOS25;
Net fpga_0_clk_1_sys_clk_n_pin LOC = H9 | IOSTANDARD=LVCMOS25;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC = H10 | IOSTANDARD=SSTL15 | PULLUP | TIG;

 

I had another error which i solve it by adding that line:

NET "xps_clk" CLOCK_DEDICATED_ROUTE = FALSE;

 

the error became a warning:


WARNING:Place:1154 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock
IOB / BUFGCTRL site pair. The clock IOB component <xps_clk> is placed at site <H9>. The corresponding BUFGCTRL
component <xps_clk_BUFGP/BUFG> is placed at site <BUFGCTRL_X0Y7>. The clock IO can use the fast path between the IOB
and the Clock Buffer if a) the IOB is placed on a Global Clock Capable IOB site that has the fastest dedicated path
to all BUFGCTRL sites, or b) the IOB is placed on a Local Clock Capable IOB site that has dedicated fast path to
BUFGCTRL sites in its half of the device (TOP or BOTTOM). You may want to analyze why this problem exists and correct
it. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <xps_clk.PAD> allowing
your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use
of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error
condition be corrected in the design.


and comilation succeed but when i compile for HW Co Sim i got that error:
 ------------------------------------------------------------------------
ERROR:HWCoSim - Program 'xflow' reported the following errors:
--------------------------------------------------------------------------------
ERROR:ConstraintSystem:59 - Constraint <NET "xps_clk" CLOCK_DEDICATED_ROUTE =
FALSE;> [hwcosim_top.ucf(106)]: NET "xps_clk" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...
--------------------------------------------------------------------------------
ERROR:HWCoSim - Program 'xflow' returned with a non-zero exit code 1.

 

 

 

Please help me to solve that mapping error as i need the map report.

 

Thanks,

Shereen

 

 

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