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Observer michelle
Observer
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Registered: ‎09-29-2018

tpg and dp1.4 IP not generating image

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Hi,

I have kcu105 with DP1.4 FMC card. I followed the example design of displayport1.4 user guide and implemented txrx pass through on kcu105. It works fine. Then I takes out RX path and it also works fine with tx only and av_pat_gen is used in the example to generate test pattern.

Then I replaced the av_pat_gen with tpg which is available in IP catalog. In SDK project, I replaced the code 

Vpg_StreamSrcConfigure(DpTxSsInst.DpPtr, 0, 1);
Vpg_VidgenSetUserPattern(DpTxSsInst.DpPtr, C_VideoUserStreamPattern[pat_update]);

 

with code below to config tpg:

ComputeMandD_vidGen(((DpTxSsInst.DpPtr->TxInstance.MsaConfig[0].PixelClockHz / 1000) /
DpTxSsInst.DpPtr->TxInstance.MsaConfig[0].UserPixelWidth));
tpg_Config->PixPerClk = XDp_ReadReg(DpTxSsInst.DpPtr->Config.BaseAddr,(XDP_TX_USER_PIXEL_WIDTH));
Status = XV_tpg_CfgInitialize(&tpg, tpg_Config, tpg_Config->BaseAddress);
if(Status != XST_SUCCESS)
{
xil_printf("ERR:: TPG Initialization failed %d\r\n", Status);
return(XST_FAILURE);
}
XV_tpg_Set_height(&tpg, DpTxSsInst.DpPtr->TxInstance.MsaConfig[0].Vtm.Timing.VActive);
XV_tpg_Set_width(&tpg, DpTxSsInst.DpPtr->TxInstance.MsaConfig[0].Vtm.Timing.HActive);
XV_tpg_Set_colorFormat(&tpg, DpTxSsInst.DpPtr->TxInstance.MsaConfig[0].ComponentFormat);
XV_tpg_Set_bckgndId(&tpg, C_VideoUserStreamPattern[pat_update]); //pattern
XV_tpg_Set_ovrlayId(&tpg, 0);
XV_tpg_WriteReg(tpg_Config->BaseAddress, XV_TPG_CTRL_ADDR_AP_CTRL, 0x81);
xil_printf(".");

 

All execution went though without error but no image is out. I used ila to check internal signal. Here's one question I have:

When config TPG IP in block design, I have to select samples per clock to 4 in order to match bus connection to dptxss. However, in the test case, I used vidmode of 800x600 60p. The pixel clock is 40MHz and only use one lane. That means tpg should just use one sample per clock. As shown in the code above, I tried to modify the tpg config sample per clock value to 1 based on dp user pixel width. It doesn't work as I found out later that the samples/clock is hw configured and can't be updated.  From ila capture, I still see the tlas (end of line) signal is still on for every 200 samples, meaning it is still 4samples per clock. This is a conflict with dptxss setting. 

Could you give suggestions on how to handle this? In addition, I can see data on on dpss link_tx_axis4_lane0 and lane1 lower 16 bits. I wonder why nothing is on screen (link status check is good).

Another question is that as a comparison, I checked lane status using ila in the project with old av_pat_gen IP, I also saw lane0 and lane1 has data. Shouldn't the active lane is 1?

Thanks!

Regards,

Michelle

 

ILA1_tpg_800x600_tlast.JPG
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Moderator
Moderator
283 Views
Registered: ‎11-09-2015

Re: tpg and dp1.4 IP not generating image

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HI @michelle,

Sorry about the delay. Next time you should post your topic directly to the Video Board (it was moved from the original board your posted on).

Yes this is correct, the DP IP will have the input changing (speaking of pixel per clock or data width) depending on how many lanes you are using while the Test Pattern generator as a fixed configuration.

You might want to keep using the pattern generator from the example design or you might.

For a TX only design, you can generate the one for ZCU102. You will see the use of a pixel remapper (which is expected to be done by the user).

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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4 Replies
Observer michelle
Observer
328 Views
Registered: ‎09-29-2018

Re: tpg and dp1.4 IP not generating image

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it seems dptxss has max lanes of 4 but can support lane of 1 or 2.

However, for tpg, once 4 samples/clock is selected in IP configuration, it can't be updated dynamically. Please confirm if it's true.

I'm trying to see if a video data width converter could help here. Please let me know if there's better suggestion.

 

Thanks and Regards,

Michelle

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Observer michelle
Observer
310 Views
Registered: ‎09-29-2018

Re: tpg and dp1.4 IP not generating image

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I got it working though software workaround. TPG is still 4 samples per clock. The hactive value setting for tpg is multiplied by a ratio. The ratio is 4 for user pixel width of 1. 

Still I would like to get a confirmation if the samples/clock can be modified on the fly.

 

Thanks and Regards,

Michelle

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Moderator
Moderator
284 Views
Registered: ‎11-09-2015

Re: tpg and dp1.4 IP not generating image

Jump to solution

HI @michelle,

Sorry about the delay. Next time you should post your topic directly to the Video Board (it was moved from the original board your posted on).

Yes this is correct, the DP IP will have the input changing (speaking of pixel per clock or data width) depending on how many lanes you are using while the Test Pattern generator as a fixed configuration.

You might want to keep using the pattern generator from the example design or you might.

For a TX only design, you can generate the one for ZCU102. You will see the use of a pixel remapper (which is expected to be done by the user).

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Moderator
Moderator
200 Views
Registered: ‎11-09-2015

Re: tpg and dp1.4 IP not generating image

Jump to solution

HI @michelle,

Do you have any updates on this?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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