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Observer taylor91
Observer
386 Views
Registered: ‎01-03-2019

two mipi_rx_dphy in same bank

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BOARD:ZC102,

when i use two mipi_rx_dphy in same bank(BANK 65),there are some critical warning:

[Vivado 12-2285] Cannot set LOC property of instance 'u_mipi_dphy0/u_mipi_dphy_rx/inst/mipi_dphy_0_rx_support_i/slave_rx.mipi_dphy_0_rx_hssio_i/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst'... Instance u_mipi_dphy0/u_mipi_dphy_rx/inst/mipi_dphy_0_rx_support_i/slave_rx.mipi_dphy_0_rx_hssio_i/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst can not be placed in PLL of site PLL_X0Y2 because the bel is occupied by u_mipi_dphy1/u_mipi_dphy_rx/inst/mipi_dphy_1_rx_support_i/slave_rx.mipi_dphy_1_rx_hssio_i/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/GEN_PLL_IN_IP_USP.plle4_adv_pll0_inst(port:). This could be caused by bel constraint conflict [/work/wproject/isp/fe/lvyongzhi/isp/vc0768_isp_zynq/fpga/vivado_2017_3_prj/sub_prj/avtop_prj/avtop_fpga_test_with_sif/avtop_sif.srcs/sources_1/ip/mipi_dphy_0/ip_0/mipi_dphy_0_hssio_rx.xdc:135]

please help me with my questaion

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
295 Views
Registered: ‎03-30-2016

Re: two mipi_rx_dphy in same bank

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Hello Taylor @taylor91 

1. Regarding XCI. Your understanding is correct, by default MIPI D-PHY is using PLL on PLL_X0Y2.
(a) you can change PLL placement for other IP to PLL_XOY3
(b) or you can opt to generate one IP as "Include Shared Logic in core" and other as "Include Shared Logic in example design".
-- Doing this will reduce the PLL usage on your design, but you need to modify the clock connectivity between MIP D-PHY module your design, so they can share the clock resources. (Please see : PG202 Chapter3 , Shared Logic in design)


2. Please do not use MIPI D-PHY from 2017.3. It is recommended to use MIPI D-PHY RX IP from Vivado to 2018.3.
Please see also the following Answer Record
https://www.xilinx.com/support/answers/71582.html
https://www.xilinx.com/support/answers/70581.html

Thanks & regards
Leo

5 Replies
Xilinx Employee
Xilinx Employee
343 Views
Registered: ‎03-30-2016

Re: two mipi_rx_dphy in same bank

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Hello @taylor91 

1. Could you please share your XCI files for both MIPI CSI-2 RX IP ?
    - I want to check the Master/Slave clock configuration
    - Pin assignment
2. Do you have any other IP implemented on bank65 IO ?

Thanks & regards
Leo

 

Observer taylor91
Observer
302 Views
Registered: ‎01-03-2019

Re: two mipi_rx_dphy in same bank

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DphyMIPI D-PHY 4.0 xdc file(Automatically generate)  as follows:

dphy0  pin

# file: mipi_dphy_0_hssio_rx.xdc
# (c) Copyright 2013 - 2015 Xilinx, Inc. All rights reserved.

# PART OF THIS FILE AT ALL TIMES.
set_false_path -to [get_pins -hier *sync_flop_0*/D]

########### Set the DIfferential IO standard from the supported Differential IO standards###############
set diff_std MIPI_DPHY_DCI


######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AH7 [get_ports clk_rxp]
set_property DATA_RATE DDR [get_ports clk_rxp]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports clk_rxp]


create_clock -period 2.000 [get_ports clk_rxp]
##create_generated_clock -divide_by 4 -source [get_ports clk_rxp] -invert [get_pins -hier -filter name=~*bs_top_inst/u_rx_bs/RX_BS[13].rx_bitslice_if_bs/FIFO_WRCLK_OUT]
######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AH6 [get_ports clk_rxn]
set_property DATA_RATE DDR [get_ports clk_rxn]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports clk_rxn]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AG8 [get_ports data_rxp0]
set_property DATA_RATE DDR [get_ports data_rxp0]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxp0]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AH8 [get_ports data_rxn0]
set_property DATA_RATE DDR [get_ports data_rxn0]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxn0]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AD7 [get_ports data_rxp1]
set_property DATA_RATE DDR [get_ports data_rxp1]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxp1]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AD6 [get_ports data_rxn1]
set_property DATA_RATE DDR [get_ports data_rxn1]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxn1]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AE8 [get_ports data_rxp2]
set_property DATA_RATE DDR [get_ports data_rxp2]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxp2]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AF8 [get_ports data_rxn2]
set_property DATA_RATE DDR [get_ports data_rxn2]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxn2]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AE7 [get_ports data_rxp3]
set_property DATA_RATE DDR [get_ports data_rxp3]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxp3]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AF7 [get_ports data_rxn3]
set_property DATA_RATE DDR [get_ports data_rxn3]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxn3]

 

set_property PHASESHIFT_MODE LATENCY [get_cells -hierarchical *plle*]
########### Use the below mentioned constraints to fix Timing Violations on Bitslice Inputs###############
#set_property -name CLKOUT0_PHASE -value -90.000 -objects [get_cells *_inst/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/plle3_adv_pll0_inst]
#set_multicycle_path -from [get_clocks -of_objects [get_pins *_inst/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/plle3_adv_pll0_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins *_inst/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL*.bs_ctrl_inst/*_BIT_CTRL_OUT*]] 2

set_property LOC PLL_X0Y2 [get_cells -hier -filter {REF_NAME =~ PLLE*_ADV && NAME =~ *pll0*}]

##########################################################################################

dphy1 pin:

      # file: mipi_dphy_1_hssio_rx.xdc
# (c) Copyright 2013 - 2015 Xilinx, Inc. All rights reserved.

# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set_false_path -to [get_pins -hier *sync_flop_0*/D]

########### Set the DIfferential IO standard from the supported Differential IO standards###############
set diff_std MIPI_DPHY_DCI


######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AE10 [get_ports clk_rxp]
set_property DATA_RATE DDR [get_ports clk_rxp]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports clk_rxp]


create_clock -period 2.000 [get_ports clk_rxp]
##create_generated_clock -divide_by 4 -source [get_ports clk_rxp] -invert [get_pins -hier -filter name=~*bs_top_inst/u_rx_bs/RX_BS[0].rx_bitslice_if_bs/FIFO_WRCLK_OUT]
######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AF10 [get_ports clk_rxn]
set_property DATA_RATE DDR [get_ports clk_rxn]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports clk_rxn]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AH12 [get_ports data_rxp0]
set_property DATA_RATE DDR [get_ports data_rxp0]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxp0]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AH11 [get_ports data_rxn0]
set_property DATA_RATE DDR [get_ports data_rxn0]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxn0]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AE12 [get_ports data_rxp1]
set_property DATA_RATE DDR [get_ports data_rxp1]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxp1]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AF12 [get_ports data_rxn1]
set_property DATA_RATE DDR [get_ports data_rxn1]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxn1]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AF11 [get_ports data_rxp2]
set_property DATA_RATE DDR [get_ports data_rxp2]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxp2]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AG11 [get_ports data_rxn2]
set_property DATA_RATE DDR [get_ports data_rxn2]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxn2]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AG10 [get_ports data_rxp3]
set_property DATA_RATE DDR [get_ports data_rxp3]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxp3]

######################################## I/O constraints ##############################################
set_property PACKAGE_PIN AG9 [get_ports data_rxn3]
set_property DATA_RATE DDR [get_ports data_rxn3]
################## Need to set diff_std before uncommenting the below line#############################
set_property IOSTANDARD $diff_std [get_ports data_rxn3]

set_property PHASESHIFT_MODE LATENCY [get_cells -hierarchical *plle*]
########### Use the below mentioned constraints to fix Timing Violations on Bitslice Inputs###############
#set_property -name CLKOUT0_PHASE -value -90.000 -objects [get_cells *_inst/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/plle3_adv_pll0_inst]
#set_multicycle_path -from [get_clocks -of_objects [get_pins *_inst/inst/top_inst/clk_rst_top_inst/clk_scheme_inst/plle3_adv_pll0_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins *_inst/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL*.bs_ctrl_inst/*_BIT_CTRL_OUT*]] 2

set_property LOC PLL_X0Y2 [get_cells -hier -filter {REF_NAME =~ PLLE*_ADV && NAME =~ *pll0*}]

///////////////////////////////////////////////////////////////////////////////

I think  its the constraints conflict,but how can i change it?

 

both ip i choose  include shared logic in core

Board :Zynq UltraScale+ ZCU102 Evaluation Board 

tool:vivado 2017.3

Thanks & regards

Taylor

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Xilinx Employee
Xilinx Employee
296 Views
Registered: ‎03-30-2016

Re: two mipi_rx_dphy in same bank

Jump to solution

Hello Taylor @taylor91 

1. Regarding XCI. Your understanding is correct, by default MIPI D-PHY is using PLL on PLL_X0Y2.
(a) you can change PLL placement for other IP to PLL_XOY3
(b) or you can opt to generate one IP as "Include Shared Logic in core" and other as "Include Shared Logic in example design".
-- Doing this will reduce the PLL usage on your design, but you need to modify the clock connectivity between MIP D-PHY module your design, so they can share the clock resources. (Please see : PG202 Chapter3 , Shared Logic in design)


2. Please do not use MIPI D-PHY from 2017.3. It is recommended to use MIPI D-PHY RX IP from Vivado to 2018.3.
Please see also the following Answer Record
https://www.xilinx.com/support/answers/71582.html
https://www.xilinx.com/support/answers/70581.html

Thanks & regards
Leo

Moderator
Moderator
241 Views
Registered: ‎11-09-2015

Re: two mipi_rx_dphy in same bank

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Hi @taylor91 ,

Do you have any updates on this?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer taylor91
Observer
214 Views
Registered: ‎01-03-2019

Re: two mipi_rx_dphy in same bank

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thanks for your solution

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