UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Participant hananz
Participant
823 Views
Registered: ‎02-23-2014

two video phy on the same bank

Jump to solution

Hi,

Is it possible to have 2 video phy (HDMI, separated channels for RX and TX ) on the same bank?

I know that there is a single configuration for both on the same core - I need a reference design to check separated rx and tx channels.

I'm customizing the HDMI rx and tx reference design, and at the bit stream stage there is the following error

 
********************************************************************

[DRC UCIO-1] Unconstrained Logical Port: 6 out of 36 logical ports have no user assigned specific location constraint (LOC).
This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity
 or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify
 all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  
 To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].
 NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a  pre-hook for write_bitstream step for the implementation run.  
 Problem ports: HDMI_TX_DAT_N_OUT[2:0], and HDMI_TX_DAT_P_OUT[2:0].

*******************************

 
and the following critical warning

 
****

[Vivado 12-2285] Cannot set LOC property of instance 'exdes_i/vid_phy_controller_1/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.exdes_vid_phy_controller_1_0_gtwrapper_gtwizard_gthe4_ins/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST'
... Instance exdes_i/vid_phy_controller_1/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.exdes_vid_phy_controller_1_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST can not be
placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y4 because the bel is occupied by exdes_i/vid_phy_controller_0/inst/gt_wrapper_inst/inst/gen_gtwizard_gthe4_top.exdes_vid_phy_controller_0_0_gtwrapper_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].
GTHE4_CHANNEL_PRIM_INST(port:). This could be caused by bel constraint conflict ["d:/WORK/HDMI/hdmi_fmc/hdmi_board_only/hdmi_board_only.srcs/sources_1/bd/exdes/ip/exdes_vid_phy_controller_1_0/ip_0/synth/exdes_vid_phy_controller_1_0_gtwrapper.xdc":68]

*******

Tnx

Hanan

Tags (2)
0 Kudos
1 Solution

Accepted Solutions
Scholar jmcclusk
Scholar
1,069 Views
Registered: ‎02-24-2014

Re: two video phy on the same bank

Jump to solution

There's no way to do this with separate RX and TX designs, because you are instantiating the GT primitives twice.   The only practical way to do this is to configure the HDMI core as a pass through, and then everything will fit.      Alternatively, move the RX or TX to a different quad.  

 

The basic problem is that the GT Serdes primitives have both RX and TX functions in the same block.   They can't be divided or split.

Don't forget to close a thread when possible by accepting a post as a solution.
2 Replies
Scholar jmcclusk
Scholar
1,070 Views
Registered: ‎02-24-2014

Re: two video phy on the same bank

Jump to solution

There's no way to do this with separate RX and TX designs, because you are instantiating the GT primitives twice.   The only practical way to do this is to configure the HDMI core as a pass through, and then everything will fit.      Alternatively, move the RX or TX to a different quad.  

 

The basic problem is that the GT Serdes primitives have both RX and TX functions in the same block.   They can't be divided or split.

Don't forget to close a thread when possible by accepting a post as a solution.
Moderator
Moderator
773 Views
Registered: ‎10-04-2017

Re: two video phy on the same bank

Jump to solution

@hananz,

 

Is everything clear for you? If yes, can you close the topic by marking @jmcclusk's solution as the accepted solution?

 

If not, please let us know what needs further explanation.

 

Regards,

Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
0 Kudos