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979 Views
Registered: ‎03-03-2017

v_tpg simulation clocks

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Hi, I have opened the v_tpg example design in Vivado 2018.1 and was wondering why the aclk frequency was chosen to be 37.125MHz.   I wanted to use this to simulate an RTL block that will examine AXI video coming out of a TPG and I was hoping to use an AXI clock of 150MHz.   When I tried setting the ACLK to the 148.5MHz instead of the 37.125 then the TPG never started outputting video data like it used to at around 6ms.

 

Can somebody help me figure out what needs to be changed in the testbench to allow me to use a faster ACLK?

 

Thanks.

Tim

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Moderator
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1,233 Views
Registered: ‎11-09-2015

Re: v_tpg simulation clocks

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Hi @tim_severance,

 

I tried to change the frequency in the test bench of the Video Beginner Series 4: Simulation with the Xilinx TPG IP to 200MHz and I can still output data from the TPG.

 

It might be something in the test bench of the example design which is not relying on signal status but only on simulation times for the original clock.

 

Hope that helps,

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar watari
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939 Views
Registered: ‎06-16-2013

Re: v_tpg simulation clocks

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Hi @tim_severance

 

According to your explanation, this test bench is expected common multiple.

 

37.125[MHz] : 148.5[MHz] = 1 : 4

 

Also, generally, test bench for video signal works fine with vertical synchronous signal.

ex. vertical synchronous register for output enable signal.

 

In your case, I suggest to use an AXI clock which is same as ACLK or common multiple.

It is reasonable frequency for simulation. not real world.

 

Best regards,

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Registered: ‎03-03-2017

Re: v_tpg simulation clocks

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@watari,

   Do you know if there is any documentation on the testbemch that comes with the example design?    I am trying to figure out why the faster clock I tried did not allow the TPG to start.   I really need a higher speed testbemch so I can simulate a few full video framers to test an RTL block I am developing.  

 

Thanks for any help. 

 

Tim

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Scholar watari
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Registered: ‎06-16-2013

Re: v_tpg simulation clocks

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Hi @tim_severance

 

Sorry. I don't know any document about like this test bench.

I explained it from my experience about ASIC and FPGA design.

Of cause I know and understand your situation (a few video frames).

However it is difficult without an analyze of specification of TPG.

 

Sorry for the inconvenience.

 

Best regards,

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Registered: ‎11-09-2015

Re: v_tpg simulation clocks

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Hi @tim_severance,

 

The example design for the TPG is mainly used just to verify the behaviour of the core but without really any real use case (as it is not ouputting on a monitor).

 

I do not see any reason why it wouldn't work. I haven't tried in simulation but at least in HW I was able to run it at 200MHz.

 

Did you try to change the frequency in the Video Beginner Serie I have written?

 

I think which could be causing the issue might be if you are running post-synthesis simulation. In this case, you might remember to change the frequency in the BD settings (for the clock input port).

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Moderator
Moderator
1,234 Views
Registered: ‎11-09-2015

Re: v_tpg simulation clocks

Jump to solution

Hi @tim_severance,

 

I tried to change the frequency in the test bench of the Video Beginner Series 4: Simulation with the Xilinx TPG IP to 200MHz and I can still output data from the TPG.

 

It might be something in the test bench of the example design which is not relying on signal status but only on simulation times for the original clock.

 

Hope that helps,

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**