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Scholar beandigital
Scholar
573 Views
Registered: ‎04-27-2010

video phy reset

Hi

I am using the video phy with HDMI TX IP on a Kintex 7 device (GTX). I have a question regarding the reset to the GTX. I can see in the initialisation code that the reset gets set to the PLL. But it doesnt seem to be coming out of reset.I have a stable clock on the reference clock and a HDMI cable plugged in. So what will cause it to be released from reset? Thanks

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5 Replies
Moderator
Moderator
538 Views
Registered: ‎10-04-2017

Re: video phy reset

Hi @beandigital,

 

 

It sounds like you may have a clocking problem. 

Can you confirm that the other clocks in your system are running/connected properly? 

  • s_axi_cpu_aclk
  • s_axis_video_aclk
  • s_axis_audio_aclk (not required)
  • link_clk
  • video_clk

For your reference clock are you selecting the correct reference clock? North/South/0/1? 

Do you have any output status in the log? 

 

Thank you,

Sam

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
Scholar beandigital
Scholar
522 Views
Registered: ‎04-27-2010

Re: video phy reset

Hi Sam

I am using GTREFCLK1. I see that in the PHY initialization that the clock buffer gets disabled. In then is enabled in a tx connect event. Is this when the cable is plugged in? I have a cable plugged in but I dont think that this clock is running. The actual clock is running into the FPGA, but I think that its still disabled. Thanks

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Scholar beandigital
Scholar
517 Views
Registered: ‎04-27-2010

Re: video phy reset

So it seems reading the manual that an interrupt is generated when the cable is plugged/unplugged. But if I have the cable connected to start with then how does the buffer get enabled? Is an interrupt still generated?
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Moderator
Moderator
496 Views
Registered: ‎10-04-2017

Re: video phy reset

Hi @beandigital,

 

The design should work regardless of whether you start with the cable plugged in or not. 

Can you provide any logs or information on the state of initialization? This will help us narrow down the issue faster.

 

If you can not provide logs, my suggestion is to put an ILA on the clock/buffer to confirm that you are correct about the clock and reset.

 

-Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
2018-11-29 15_35_22-xcovnc102_24 (xcovnc102_24 (samk)) - VNC Viewer.png
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Moderator
Moderator
460 Views
Registered: ‎11-09-2015

Re: video phy reset

Hi @beandigital,

Do you have any updates on this? Were @samk's replies enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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