11-27-2018 02:04 PM
I am using the video phy with HDMI TX IP on a Kintex 7 device (GTX). I have a question regarding the reset to the GTX. I can see in the initialisation code that the reset gets set to the PLL. But it doesnt seem to be coming out of reset.I have a stable clock on the reference clock and a HDMI cable plugged in. So what will cause it to be released from reset? Thanks
11-28-2018 11:02 AM
It sounds like you may have a clocking problem.
Can you confirm that the other clocks in your system are running/connected properly?
For your reference clock are you selecting the correct reference clock? North/South/0/1?
Do you have any output status in the log?
11-29-2018 01:34 AM
I am using GTREFCLK1. I see that in the PHY initialization that the clock buffer gets disabled. In then is enabled in a tx connect event. Is this when the cable is plugged in? I have a cable plugged in but I dont think that this clock is running. The actual clock is running into the FPGA, but I think that its still disabled. Thanks
11-29-2018 01:44 AM
11-29-2018 02:37 PM
The design should work regardless of whether you start with the cable plugged in or not.
Can you provide any logs or information on the state of initialization? This will help us narrow down the issue faster.
If you can not provide logs, my suggestion is to put an ILA on the clock/buffer to confirm that you are correct about the clock and reset.
12-04-2018 04:12 AM
Do you have any updates on this? Were @samk's replies enough for you?
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