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Newbie
Newbie
3,328 Views
Registered: ‎09-21-2008

warning messages when verifing the RTL

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#( W-RTL-0029): Cannot calculate a constant throughput/latency for the design because a for-loop is guarded by the if-statement 'ac_tmp_1'.

#( W-RTL-0022): Cannot register inputs and generate "push-mode" interface because the design does not have a constant throughput.

 

When I using the AccelDsp9.2.01.102 to run the 'verify the RTL' step,disappeared the above warning messages inTcl console.what can I do to resolve the problem.

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Xilinx Employee
Xilinx Employee
3,504 Views
Registered: ‎08-21-2007

Re: warning messages when verifing the RTL

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I might not understand your question, but if a design doesn't have a constant data flow (the number of clock cycles to compute an output is not constant - it depends on an input) then AccelDSP can not report the number of clocks it takes to compute each result until after Verify -rtl is completed.  In addition, the push mode interface can only be used for designs where it takes the same number of clock cycles to compute each output.  In this case the full handshake interface will be generated by AccelDSP.

 

Tim

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Xilinx Employee
Xilinx Employee
3,505 Views
Registered: ‎08-21-2007

Re: warning messages when verifing the RTL

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I might not understand your question, but if a design doesn't have a constant data flow (the number of clock cycles to compute an output is not constant - it depends on an input) then AccelDSP can not report the number of clocks it takes to compute each result until after Verify -rtl is completed.  In addition, the push mode interface can only be used for designs where it takes the same number of clock cycles to compute each output.  In this case the full handshake interface will be generated by AccelDSP.

 

Tim

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