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Observer m.yaghmai
Observer
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Registered: ‎12-04-2018

xapp1291 Reference design using Vivado Design Suite 2018.2

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Hi,

First of all I am totally a newbie, so nothing is too basic for me. I have the K705 Evaluation board in hand and I want to implement video processing subsystem reference design on it.

The document for this reference design is XAPP1291 (v1.0.1) July 22, 2016 using Vivado Design Suite 2016.2 but I have Vivado Design Suite 2018.2 installed.

When I follow the steps in the document I am facing multiple issues which after programming the FPGA does not give me any output and I am not sure what is the cause. My issues are as following :  

1. Based on the first step in the document I need to switch between "xmd" shell and xsct shell which I was not able to do so. I googled and it was saying there is no more xmd shell and instead we have xsdb but I was receiving error trying to switch to xsdb as well so I decided to go with the second approach which was creating a design from scratch. ( Does this make sense or I did not know how to use the scripts ? )

2. When I was creating the design from scratch, I received so many warnings and critical warnings. I googled and for most of them it was saying that it is ok to ignore the warnings. Example of the warnings :

  • [BD 41-1731] Type mismatch between connected pins: /mixer_reset/gpio_io_o(undef) and /v_mix_0/ap_rst_n(rst)
  • [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /memory_ss/axi_mem_intercon/s03_couplers/auto_us_cc_df/S_AXI(0) and /memory_ss/axi_mem_intercon/s03_couplers/s03_regslice/M_AXI(1)
  • [Synth 8-350] instance 'gtnorthrefclk_buf' of module 'vprd_gtnorthrefclk_buf_0' requires 4 connections, but only 3 given ["E:/Mana/xapp1291/vprd_project/vprd.srcs/sources_1/bd/vprd/synth/vprd.v":9340]
  • [Synth 8-3848] Net LED1 in module/entity vprd does not have driver. ["../xapp1291/vprd_project/vprd.srcs/sources_1/bd/vprd/synth/vprd.v":8671]
  • [Timing 38-316] Clock period '100.000' specified during out-of-context synthesis of instance 'vprd_i/axis_switch_0' at clock pin 'aclk' is different from the actual clock period '3.333', this can lead to different synthesis results.
  • [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
  • [Synth 8-589] replacing case/wildcard equality operator === with logical equality operator == ["../xapp1291/vprd_project/vprd.srcs/sources_1/bd/vprd/ip/vprd_v_proc_ss_0_0/bd_0/ip/ip_5/hdl/verilog/bd_870e_ltr_0_AXIvideo2MultiPixStr.v":1084]

I am not sure if they cause any issues or not. So I proceeded with the steps and generated the bitstream and then exported hardware(.elf file).

When I wanted to generate the SDK project and running the provided tcl script (vprd vprd_wrapper.hdf) I received the following errors which won’t let the script to generate the .elf file ( So I commented out all those Report output lines in the code regarding HDMI to be able to proceed). ( Here is just two of so many errors I was receiving)

../src/system.c: In function 'XSys_ReportSystemInfo':

../src/system.c:758:3: warning: implicit declaration of function 'XV_HdmiRxSs_ReportCoreInfo'; did you mean 'XV_HdmiRxSs_ReportInfo'? [-Wimplicit-function-declaration]

   XV_HdmiRxSs_ReportCoreInfo(pInss->Hdmi.HdmiRxSsPtr);

   ^~~~~~~~~~~~~~~~~~~~~~~~~~

   XV_HdmiRxSs_ReportInfo

../src/system.c:764:3: warning: implicit declaration of function 'XV_HdmiTxSs_ReportCoreInfo'; did you mean 'XV_HdmiTxSs_ReportInfo'? [-Wimplicit-function-declaration]

   XV_HdmiTxSs_ReportCoreInfo(pOutss->Hdmi.HdmiTxSsPtr);

..\xapp1291\sdk\vprd.sdk\vprd_ref_design\Debug/../src/system.c:814: undefined reference to `XV_HdmiRxSs_ReportLinkQuality'

..\xapp1291\sdk\vprd.sdk\vprd_ref_design\Debug/../src/system.c:820: undefined reference to `XV_HdmiRxSs_ReportAudio'

..\xapp1291\sdk\vprd.sdk\vprd_ref_design\Debug/../src/system.c:824: undefined reference to `XV_HdmiRxSs_ReportInfoFrame'

collect2.exe: error: ld returned 1 exit status

make: *** [vprd_ref_design.elf] Error 1

Then I finally opened SDK 2018.2 and programmed the board using the vprd_wrapper.bit and vprd_wrapper.mmi. (I attached a picture of the GPIO LEDs so you can see which ones are on).

Then right click on "vprd_ref_design" and Run > Launch on Hardware . Then here comes the problem. After seeing the info on the terminal regarding HDMI RX and TX , I am receiving errors and then it does not proceed any further till I hit any key which sends me to the Help Menu. Please find the screenshot from the error.

->Output Resolution set to 1920x1080@60Hz
OUTSS ERR:: Error programming External Clock Generator (SI 5324)

Would you please help me with that? I already spent 3 days trying to figure it out and I need to make it up and running for the end of this week.

Thanks!

Run as hardware debug.PNG
K507.jpg
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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HI @m.yaghmai,

You should be able to get the input from HDMI on the output. Also there is a test pattern generator so you should be able to change the pattern displayed.

If you are only looking for HDMI you might want to use the example design integrated in vivado (this way you can use 2018.2). Just refer to chapter 5 of pg236

The way to move the xapp from 2016.2 to 2018.2 is to start by building the vivado +sdk design, make sure it still work. Then open the vivado project IPs in 2018.2 and make all the changes required by the tool.

I would recommend you to use the example design integrated in vivado

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Hi @m.yaghmai,

Xapps are supported for a specific vivado version. You might want to use this version first (i.e. 2016.2 in your case). Then once it is working you can switch to a newer version (by moving the full vivado project) but you need to be aware that some updates might be required on your side.

You should be able to use the pre-built images (.elf and .bit from the ready to download folder) with xsct as a start but it will not give you the complete project.

In summary, I recommend to start with 2016.2 and move to 2018.2 later.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer m.yaghmai
Observer
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Registered: ‎12-04-2018

Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Hello,

Thank you for your reply. I have downloaded Vivado 2016.2 and used the ready_for_download files BUT when I run source run.tcl script, I am receiving a warning as following : 

 WARNING: Processor Version 0x23 - UnSupported Version, New Features May Not Work ( you can also see it in the attachment)

At the end I was expecting to see "vprd.sdk" in the project that is created(vprd_project) but there is no "vprd.sdk" directory and of course no "vprd_wrapper.elf".

Then I tried to generate .bit file using Vivado and I am receiving this error:

source ./design/setup.tcl
# create_project vprd ./vprd_project -part xc7k325tffg900-2
WARNING: [Device 21-436] No parts matched 'xc7k325tffg900-2'
ERROR: [Coretcl 2-106] Specified part could not be found.

Then I checked if I have K705 board in Vivado Design Suite and I don't have it. I already got all the licenses that got mentioned in the tutorial. So does that mean Vivado 2016.2 does not support that board?  How can I add it ?

Thank you in advance!

run_tcl1.PNG
run_tcl2.PNG
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Hi @m.yaghmai,

2016.2 supports the KC705 but you need 2 things:

1. Install a system edition of Vivado (the KC705 will not be present in the webpack edition)

2. A license for the KC705 of Kintex devices (usually you just need a license for the system edition).

You should be able to generate an evaluation license for the system edition.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer m.yaghmai
Observer
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Registered: ‎12-04-2018

Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Thank you very much ! Now I have K705 board in the list , I used the ready_for_download script ,so after running run.tcl script , on the serial port terminal I am seeing that the connection has established.

I started playing with the help menu options but for Picture mode I am getting this error :


ERR:: NO INPUT DETECTED - Picture Settings Menu Disabled

Is there any way that I can change the images that I see ? or make the HDMI source display updates live ?

Also you mentioned that after make it work on Vivado 2016.2 then there is way to make it work on Vivado 2018.2. I tried to google it but I did not find anything. Would you please help me with that?

Thank you

putty_output.PNG
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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HI @m.yaghmai,

You should be able to get the input from HDMI on the output. Also there is a test pattern generator so you should be able to change the pattern displayed.

If you are only looking for HDMI you might want to use the example design integrated in vivado (this way you can use 2018.2). Just refer to chapter 5 of pg236

The way to move the xapp from 2016.2 to 2018.2 is to start by building the vivado +sdk design, make sure it still work. Then open the vivado project IPs in 2018.2 and make all the changes required by the tool.

I would recommend you to use the example design integrated in vivado

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer m.yaghmai
Observer
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Registered: ‎12-04-2018

Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Hi @florentw,

I am not seeing anything as HDMI source output. I have the HDMI connected to my pc and what it should show is my PC's screen, right ?

I am seeing the layers (1,2,3 and logo layer) but the for master layer I just have a plain blue layer! When I switch the input of HDMI to TPG, I can see the generated test pattern as my master layer. Is there any way to debug the HDMI using the source not TPG ?

I also tried to read and implement chapter 5 of HDMI2.0 RX subsystem document. Well I could go over the steps but when I programmed the board with the example design I cannot see anything and LED0 does not turn on !

Thank you

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Moderator
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Registered: ‎11-09-2015

Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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HI @m.yaghmai,

Yes you should be able to see the HDMI input from your machine. Not sure why is it not working. But in 2016.2 the HDMI IP was not as stable as now, so might be an issue with the IP in 2016.2.

This is why I recommended you to use the example design for HDMI from 2018.2. You might want to create a new topic for debugging this example design. It will be a better start for you.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer m.yaghmai
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Registered: ‎12-04-2018

Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Oh I see your point! Sure I will create a new topic. So I should replace rx subsystem from the reference design with the example design on 2018.2 ? (Which I am not sure how to do so)

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Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Hi @m.yaghmai

So I should replace rx subsystem from the reference design with the example design on 2018.2 ?

> I am not sure what is your question here. For the moment I recommend you to oupen the HDMI TX/RX Subsystem example design. Make sure that it works for you. Then if you want to use the video mixer, add it as a next step.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer m.yaghmai
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Registered: ‎12-04-2018

Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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I thought when you say use the example design you mean to open it in Vivado and then somehow replace the RX subsystem in the reference design that I already have with this example design of RX.

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Registered: ‎11-09-2015

Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Hi @m.yaghmai,

No the recommendation is to work on the HDMI example design as a starting point. Then modify it


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Hi @m.yaghmai,

Happy New Year 2019!

Do you have any updates on this?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer m.yaghmai
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Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Happy new year to you too :) !

 

I was not able to make the HDMI example work. I was going over the chapter 5 of HDMI 1.4/2.0 RX Subsystem and on page 61 we are choosing HDMI receiver subsystem from the catalog and on the next page it got mentioned to customize transmitter which is so confusing , because if I am adding HDMI receiver so I need to customize the receiver or vise versa ! So what I have done was to choose HDMI receiver then customized it then opened the example design for it. Afterwards, a new vivado lunched and after the example design got loaded, I received 70 warnings such as : 

  • [IP_Flow 19-3153] Bus Interface 'aud_clk': ASSOCIATED_BUSIF bus parameter is missing.
  • [Vivado 12-3670] The generate_synth_checkpoint property should only be queried on the file object representing this IP. Use the get_files command to access file objects.
  • [Memdata 28-79] No processor module instance paths found in the source hierarchy. Please make sure that the source hierarchy is correctly established for the current 'top' module and the processor modules are part of this hierarchy.

I tried to google the warnings but I did not get any answers except somebody mentioned that it is ok to ignore the warning regarding the aud_clk.

I ran Synthesis but I got more warnings such as:

  • [Constraints 18-5210] No constraint will be written out.

Then I ran the Implementation and more warnings popped up + 4 critical warnings (which I read that it is ok to ignore them)

I continued and ran Generate bitstream and exported hardware and went over steps 10 to 15. On step 16 again i see that I need to import Transmitter subsystem driver which I am not sure why not receiver ? 

So this is the point that I stopped and did not proceed further.

Thank you very much for your help in advance.

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Registered: ‎11-09-2015

Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Hi @m.yaghmai,

There is an issue in the PG for the HDMI receiver. This was already reported and should be fixed in the next version of the docuementation. Each time the "transmitter" is written in the steps for the "HDMI receiver IP" example design, just read "HDMI receiver IP"

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer m.yaghmai
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Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Hi @florentw

Thank you for the reply. It took me some time to proceed because my pc was not recognizing the FPGA.

So, I went over all steps from chapter 5 of HDMI 1.4/2.0 RX Subsystem document. I downloaded the bitstream to the FPGA and I saw that the LEDs turned on and off. Then I downloaded the software .elf to the FPGA. Now I am not sure how can I test it through the hardware to make sure if it is working properly ?

Bests

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Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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HI @m.yaghmai,

Do you see any output message on the UART? Do you have any output on your monitor?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer m.yaghmai
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Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Yes I see messages on UART , which is a menu and then I can see the info which shows that the RX is ready as can be seen here:

GT status
---------
RX reference clock frequency: 74246144 Hz
DRU reference clock frequency: 125000000 Hz
TX: CPLL
RX: QPLL
TX state: idle
RX state: ready

RX stream is up
Color Format: YUV_422
Color Depth: 12
Pixels Per Clock: 2
Mode: Progressive
Frame Rate: 30Hz
Resolution: 1920x1080@30Hz
Pixel Clock: 74250000

I have a Test Pattern Generator connected to it but I don't have any output on the monitor.

Just to make sure, for the RX subsystem that I implemented on the FPGA is what controls the RX on the FMC card. And on the FMC card I connect the RX to the source ( Test Pattern Generator in my case ) and the TX on the FMC board to a monitor(sink). Right?

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Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Hi @m.yaghmai,

Yes it seems correct.

What happen if you press i? It should display the system information


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer m.yaghmai
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Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Yes it shows the info as following:

-----
Info
-----

------------
HDMI RX SubSystem
------------

->HDMI RX Subsystem Cores
: HDMI RX
HDMI RX version : 03.00 (0400)

HDMI RX Mode - HDMI
------------
HDMI RX timing
------------
Color Format: YUV_422
Color Depth: 12
Pixels Per Clock: 2
Mode: Progressive
Frame Rate: 30Hz
Resolution: 1920x1080@30Hz
Pixel Clock: 74250000

HSYNC Timing: hav=1920, hfp=88, hsw=44(hsp=1), hbp=148, htot=2200

VSYNC Timing: vav=1080, vfp=04, vsw=05(vsp=1), vbp=036, vtot=1125

VIC: 34
Scrambled: 0
Link quality
---------
Link quality channel 0 : excellent (0)
Link quality channel 1 : excellent (0)
Link quality channel 2 : excellent (0)
Audio
---------
Format : L-PCM
Channels : 8
ACR CTS : 140766
ACR N : 11648
Infoframe
---------
RX header: 4A0A0184

------------
HDMI PHY
------------
VPhy version : 02.02 (0000)

GT status
---------
RX reference clock frequency: 74246144 Hz
DRU reference clock frequency: 125000000 Hz
TX: CPLL
RX: QPLL
TX state: idle
RX state: ready

QPLL settings
-------------
M : 1 - N : 80 - D : 8

CPLL settings
-------------
M : 0 - N1 : 0 - N2 : 0 - D : 0

RX MMCM settings
-------------
Mult : 16 - Div : 1 - Clk0Div : 32 - Clk1Div : 16 - Clk2Div : 32

TX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

DRU Settings
-------------
Version : 7
DRU is disabled

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Xilinx Employee
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Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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@m.yaghmai

From your log information, it seems that you generate the RX only design, there is no TX Subsystem IP in your project. Can you generate pass-through design, and then see if it works?

Highlighted
Observer m.yaghmai
Observer
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Registered: ‎12-04-2018

Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Thank you for your help @florentw and @xud . I generated the pass-through design and i can see the test pattern on the screen that I connected.

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Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Hi @m.yaghmai,

Do you have what you wanted? If it is the case could you kindly close the topic by marking a reply as accepted solution? (it seems that you did it and then revoked the solution...)

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer m.yaghmai
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Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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@florentw Yes it worked , I was not sure which answer to mark as a solution because you gave me an answer in the middle to switch to Vivado 2016.2 which was the first solution and after couple of more questions there was another answer that helped me to see something on the screen.

I wanted to mark both as solutions but I saw it is not possible so I removed the one that I have marked to see if there is a way to choose more than one answer.

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Registered: ‎11-09-2015

Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Hi @m.yaghmai,

You are right, I discussed with @xud and my reply was the best for the initial question ;)

Thus can you mark this one as accepted solution:

https://forums.xilinx.com/t5/Video/xapp1291-Reference-design-using-Vivado-Design-Suite-2018-2/m-p/921785/highlight/true#M23208

PS: No worries, there are no competition between Xu and I. Our goal is to make sure the next member with the same question gets an answer quickly.

However, you can still give a kudos to @xud to say thank you by using the thumb up below her reply:

kudos.JPG

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer m.yaghmai
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Re: xapp1291 Reference design using Vivado Design Suite 2018.2

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Thank you very much @florentw and @xud !

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