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544 Views
Registered: ‎03-19-2017

zc702 trd design issue for tpg to hdmiout

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Dear,

Is it possible to make tpg ip directly connect to hdmiout module without via vdma?

I tried to modify zc702 trd example to make tpg directly connect to hdmiout, but failed, why?

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Explorer
Explorer
521 Views
Registered: ‎03-28-2016

Re: zc702 trd design issue for tpg to hdmiout

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Typically, if a video IP has a master AXI4-Stream output and another video IP has a slave AXI4-Stream input, then the two IP can be connected together as long as both of the AXI4-Stream interfaces follow the "Video over AXI4-Stream" protocol defined by Xilinx in UG934.

 

https://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf

 

It is the responsibility of the user to verify that connecting the two IP is appropriate.  In this case it's likely that the "hdmiout" can accept a video stream from the TPG.

 

As for why your modifications failed.  I have no idea.  You didn't provided any information.

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
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2 Replies
Explorer
Explorer
522 Views
Registered: ‎03-28-2016

Re: zc702 trd design issue for tpg to hdmiout

Jump to solution

Typically, if a video IP has a master AXI4-Stream output and another video IP has a slave AXI4-Stream input, then the two IP can be connected together as long as both of the AXI4-Stream interfaces follow the "Video over AXI4-Stream" protocol defined by Xilinx in UG934.

 

https://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_videoIP.pdf

 

It is the responsibility of the user to verify that connecting the two IP is appropriate.  In this case it's likely that the "hdmiout" can accept a video stream from the TPG.

 

As for why your modifications failed.  I have no idea.  You didn't provided any information.

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: zc702 trd design issue for tpg to hdmiout

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Hi p.ching.kuang@gmail.com,

 

Did the reply from @tedbooth helped?


If your question is answered or your issue is solved, please mark the response which helped as solution (when logged in, click on the "accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,


Florent
Xilinx Community Forums Moderator


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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