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Visitor zombi80
Visitor
4,945 Views
Registered: ‎04-20-2010

3 Input clock mux using Virtex 5

Whats the best way to create a 3 input clock mux(synchronous clocks) in Virtex5.

 

Is it okay if I use two BUFGCTRL's which might do the job, not sure if it allows to route.

 

Thanks. 

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4 Replies
Xilinx Employee
Xilinx Employee
4,923 Views
Registered: ‎11-28-2007

Re: 3 Input clock mux using Virtex 5

Using 2 BUFGCTRL (BUFGMUX) will work. Do the 3 input clocks come from the same DCM or PLL with diference frequencies and/or phases?

 

Cheers,
Jim
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Visitor zombi80
Visitor
4,912 Views
Registered: ‎04-20-2010

Re: 3 Input clock mux using Virtex 5

Yes, all the three clocks are coming out of the PLL with different frequencies and are synchronous with same phase.
BUFGMUX1 (CLK1IN,CLK2IN,TMPCLKOUT)
BUFGMUX2(CLK3IN,TMPCLKOUT,CLKOUT)
So this should be working fine, and any tips on how I insert the BUFG's as these clocks are coming from PLL, so no bufgs out of PLL or ??
 
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Xilinx Employee
Xilinx Employee
4,893 Views
Registered: ‎11-28-2007

Re: 3 Input clock mux using Virtex 5

Other than the select signal is missing, that should work. Using your example code, you can connect 3 PLL outputs directly to the CLK1IN, CLK2IN and CLK3IN ports on BUFGMUX1 and BUFGMUX2.

Cheers,
Jim
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Visitor zombi80
Visitor
4,888 Views
Registered: ‎04-20-2010

Re: 3 Input clock mux using Virtex 5

Thanks jim...
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