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Explorer
Explorer
5,378 Views
Registered: ‎07-24-2008

A question about configuration time

Hi all,

 

    Can you tell me the configurtaion time that loads .mcs file from flash to FPGA? Can I set the configuration clock (CCLK)  frequency? If the CCLK is a high frequency clock, does it can accelerate the configuration time? And is parallel load mode faster than serial load mode?

 

Thanks.

Best Regards.

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3 Replies
Teacher eteam00
Teacher
5,374 Views
Registered: ‎07-21-2009

Re: A question about configuration time

First off, the .mcs file isn't stored in the flash memory.  .MCS file format is ASCII text.  The binary data which is represented by the .mcs file is stored in the flash.

 

The configuration time depends on the FPGA you are using.  Larger devices have larger configuration data sets which take longer to load.

 

Some FPGA families permit setting a config clock frequency higher than the normal default.  If you are using a flash memory fast enough to keep up with a higher speed config clock, the config clock speed setting can cut down on configuration time considerably.

 

What you should do to learn more of the specifics is this:  for the device family in which you are interested (Virtex-6, for example), go to the documentation page for that family, find the Configuration User Guide for that family, and give it a read.  All the information you need for estimating configuration time and how to optimise configuration time should be in that document.

 

And yes, parallel configuration load mode should be faster than serial configuration modes.  See the configuration user guide mentioned above.

 

- Bob Elkind

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Instructor
Instructor
5,353 Views
Registered: ‎08-14-2007

Re: A question about configuration time

Some more points:

 

The CCLK generated in Master SPI  or other Master modes is not very precise (+/- 50% frequency).

So you are usually limited to 2/3 of the maximum clock frequency of the Flash device as the nominal

setting and then can be running as little as 1/3 of the maximum frequency.

 

Slave Serial mode is usually the easiest way to configure the part from an external device like a

microcontroller or a CPLD with connected flash memory.  In slave serial mode you can use a

more precise clock to configure the device at or near the maximum rated frequency of the FPGA,

for example 100 MHz for Virtex 5.

 

All of the parallel programming modes require you to use a lot of pins that would otherwise be

useful for I/O.  If you already need a simple generic bus interface to an on-board CPU, then

you may be able to re-use the configuration pins after configuration is complete.  Otherwise

you might find yourself buying a larger part than you really need just to get enough I/O pins.

 

Regards,

Gabor

-- Gabor
Teacher eteam00
Teacher
5,343 Views
Registered: ‎07-21-2009

Re: A question about configuration time

Here is some rewording of and elaboration on Gabor's comments...

The CCLK generated in Master SPI  or other Master modes is not very precise (+/- 50% frequency). So you are usually limited to 2/3 of the maximum clock frequency of the Flash device as the nominal setting and then can be running as little as 1/3 of the maximum frequency.

Correct.  Here is an example:

If you are targeting a 33MHz SPI flash memory, for example, you should select a 22MHz (or slower) CCLK frequency option.  The 22MHz CCLK speed could be as high as 33MHz (the SPI flash memory limit) or as low as 11MHz.  That's a 3:1 range of frequency.

Slave Serial mode is usually the easiest way to configure the part from an external device like a microcontroller or a CPLD with connected flash memory.  In slave serial mode you can use a more precise clock to configure the device at or near the maximum rated frequency of the FPGA, for example 100 MHz for Virtex 5.

Any slave configuration mode eliminates the 3:1 range of configuration clock uncertainty.

All of the parallel programming modes require you to use a lot of pins that would otherwise be useful for I/O.

This is perhaps better worded as:

All of the parallel programming modes require you to use a lot of pins that MIGHT otherwise be useful for I/O.

Most pins used in parallel configuration mode (or any configuration mode) can be used as general purpose user IO pins after configuration is complete.  You can be as clever as you like in the use of these pins, avoiding conflicts between the pre-configuration and post-configuration pin usage.  Parallel config modes involve more pins than serial config modes, of course, which increases the pin conflict avoidance effort.

If you already need a simple generic bus interface to an on-board CPU, then you may be able to re-use the configuration pins after configuration is complete.  Otherwise you might find yourself buying a larger part than you really need just to get enough I/O pins.

If you are looking for maximum possible configuration speed, then slave parallel config mode is your best option.  A conventional low-cost microprocessor or microcontroller might be hard-pressed to keep up with the 100MHz or higher maximum config clock rate.  A CPLD should have little problem maintaining the fastest config speeds.  Don't forget that you will also need a memory for configuration data storage which is fast enough to support the config frequency.

 

As usual, there is a tradeoff between performance and cost and design time.

 

Also, don't overlook such start-up delays as:

  • DRAM controller calibration and initialisation
  • PLL/DCM spin-up and lock
  • Ethernet PHY init and speed negotiation
  • etc.

It may well be that these delays would make gains from aggressive configuration speedup to be insignificant.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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