07-27-2015 06:36 AM
I have a problem when I scrube the DSP, IOB, CLK, CLB using the data stored in the Flash to correct the SEU in Virtex4 LX25 FPGA. This is my flow chart:
step1: read the state register to verify the state register
step2: read the control register to verify the control register
step3: write a 32bit data to FAR register and read FAR register to virify the FAR register
step4: scrube the DSP, IOB, CLK, CLB logic in the Virtex4 LX25 FPGA using the data stored in the Flash(I shield the LUT RAM and SRL16).
Problem: when the step4 is done, if I immediately implement the step1 the scrube programe can influence the CLB logic. But when the step4 is done, if I delay 0.1s to implement the step1 the scrube programe has no influence on CLB logic.
Is this means that I should wait a minute when I begin the next scrube process? Thank you in advance.
07-27-2015 07:08 AM
SEU mitigation as a feature was depricated in V4 (removed).
The V4 had a series of issues that prevents the feature from being supported. It is supported for those few who started using it, by special order number screened parts, and the latest revision of the IP that was created at the time. All other cases are not supported.
Simple scrubbing (re-writing the configuration) is supported, but through the IP supported by the aerospace/defense group. You must contact them directly (A/D issues are not to be discussed here in these forums).
07-28-2015 03:07 AM
Hi Lesea, Virtex4 is not supported by Soft Error Mitigation (SEM) Core, and I need to protect the Virtex4 LX25 FPGA by simple scrubbing. The configuration management engine I designed is the same as that in Correcting Single-Event Upsets in Virtex-4 FPGA Configuration Memory. I also do the fault injection experiment, and the configuration management engine can correct the faults in the Virtex4 LX25 FPGA.
On my board: digital signal A---->encode---->D/A---->A/D---->decode---->digital signal B
When I don't scrubbing the FPGA, the signal B is always the same as the signal A, so I think my board and the software in the FPGA operate well. When I scrubbing the FPGA too frequently, the signal B is not always the same as signal A(I only scrubbing the DSP, IOB, CLK, and CLB logic and I shield the LUT RAM and SRL16 logic). So I think the problem is caused by my configuration management engine.
I also find that the time between two scrubbing process can not be too short. For instance, if I delay only several clks(2.3825MHz) before the next scrubbing process, the signal B is not always the same as the signal A. But if I delay 0.1s, 1s or 10s before the next scrubbing process, the signal B is always the same as the signal A. So how can I solve the problem? I can do experiment to find the minimal time between the two scrubbing process that have no influence on my software. I want to know what causes this problem. Thank you:)