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Visitor
Visitor
8,695 Views
Registered: ‎02-10-2016

AXIS to Video out IP core's locked pin doesn't go high and No video output from the core

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I'm working on ML605 board to build a video base system.

i'm having avnet HDMI board for connecting video input to board, and having IP's such as video in to AXIS , VTC, chroma resampler, Ycrcb to RGB conveter and AXIS to Video out. all the output till AXIS to Video out are perfect, i think(seen via chipscope).

but there is no output from AXIS to Video out IP and it's locked status doesn't go high. i'm configured it master mode because there is no video processing element(such as vdma,scalar etc.) in the processing path.

vtc is configure for a resolution of 1080p.

so what is reason that the core doesn't provide video output?

 

please help me to rectify the problem..

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Xilinx Employee
Xilinx Employee
16,121 Views
Registered: ‎08-02-2011

Oh okay, good! That sounds like the timing is right, but the data is just all zeros somewhere. That's generally easier to track down with chipscope.

www.xilinx.com

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Xilinx Employee
Xilinx Employee
8,667 Views
Registered: ‎08-02-2011
Have you searched the forums for this? This particular issue is discussed quite a bit.
www.xilinx.com
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Visitor
Visitor
8,643 Views
Registered: ‎02-10-2016

yes.

 

i covered almost topics regarding this and tried all. but no result.

i'm doing it in ISE 14.6, but i got it in vivado 2014.4 for kc705.

my requirement is to work it in ML605.

 

-- there is no video processing core(vdma , scalar ) in my path.

-- so i configured AXIS to Vout IP in master mode and drive the gen_clken of VTC with '1'( do not feedbacked vtg_ce).

-- is any other critical requiremnt for this design?

 

please give valuable suggessions..

 

 

 

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Xilinx Employee
Xilinx Employee
8,609 Views
Registered: ‎08-02-2011

Oh okay, great! That's a good start.

 

Is the video source live or TPG? If it is live video, the AXIS to Video Out should be in slave mode and gen_clken connected to vtg_ce.

www.xilinx.com
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Visitor
Visitor
8,495 Views
Registered: ‎02-10-2016

it's live video.

 

first i connect as per the product guide document ie; feedbacked vtg_ce and held IP in slave mode.

at this time also no video coming at the output side but output display is getting turned ON (with out any video, i think it's because of output video clock is coming properly)

 

 

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Xilinx Employee
Xilinx Employee
8,473 Views
Registered: ‎08-02-2011

Okay yeah, if you have live video input, then you should be in slave mode with vtg_ce connected.

 

Is the display turning on and detecting some resolution? If so, this means the timing is good and it's just the data that's wrong.

 

Or if the display is toggling off/on, this often means the timing (and/or pixel clock) is wrong.

www.xilinx.com
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Visitor
Visitor
8,461 Views
Registered: ‎02-10-2016

Yeah..

the display is turned ON with no video(black screen with backlight turned ON).

what you mean by error in data? can you detail that??

 

i'm not using any custom code in my design except for the HDMI card( we used a code to convert the O/P of FMC imageon board to YUV422) .

 

i;m attaching the top level code for the reference..

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Xilinx Employee
Xilinx Employee
16,122 Views
Registered: ‎08-02-2011

Oh okay, good! That sounds like the timing is right, but the data is just all zeros somewhere. That's generally easier to track down with chipscope.

www.xilinx.com

View solution in original post

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Visitor
Visitor
8,441 Views
Registered: ‎02-10-2016

ok

thank you for your reply..

 

the problem is resolved..

i made a software reset to FMC module and the proceed , it works properly..

thank you..

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