09-03-2015 11:16 AM
I am trying to use the CARRY4 to build a delay line.According to the CARRY4 's structure on the user guide.The timing of each output (CO) should be like this:
But after I try post-route simulation, the actual result show as below:
I guess, the reason of this is the delay between two slices much longer than the delay inside of the slice.So make the 4th CO of each CARRY4 became the fastest one can reduce the overall carry chain delay.But why the second is 2nd CO?
Anyway this is just my conjectures.I am wondering is this correct?And the exact reason of this.
Thanks a lot
09-05-2015 06:27 PM
You have to be very careful with this stuff...
The outputs of the CARRY4 go through the rest of the slice structure to the routing channels, and from there to whatever you have routed them to. In post implementation simulation, the delay of the cell and the net get "lumped" together - so you can't actually see the timing at the output of the slice, but at the input pin of whatever it is connected to. Since these connections use general routing, their delays will be dependent on exactly how the router routed them. There is no way to control the router at this fine level (its only goal is to "make timing", which attempts to meet the setup time of the entire combinatorial path), so you will always end up with some "randomness" in this timing from bit to bit based on the router (and this will change from implementation run to implementation run). The only way to "control" this is to manually place the destinations and manually route the nets (which is a very painful process).
Also, the representations of the CARRY4 in the user guides and in FPGA editor are merely a logical representation - the are not actually (or necessarily) implemented that way. I know that in some technologies these are fast carry blocks, and hence there is no actual guarantee that the upper bits take more time internally than the lower bits. From block to block you will see a monotonic increase (as it goes from the carry out of one CARRY4 to the carry in of the next), but other than that, all bets are off.
09-07-2015 03:18 AM
Thanks for your reply. It is helpful.
As you said, I used manually place method to make sure the entire delay line placed in the centre of the chip and build a shield ring around it. And I also make each CO of CARRY4 and theirs sampling D-FFs are located in the same slice.
Anyway, this structure brings huge nonlinearity to the delay line based TDC.
I believe xilinx make the post-simulation timing look like that must be for some reasons.So do you know the actual structure or layout of the inside of the CARRY4?
By the way, is there any possibility to let xilinx to build a specialized tapped-delay-line into FPGA chip? Just like IODELAY's delay line?