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Visitor
Visitor
9,241 Views
Registered: ‎04-23-2014

Accessing Block memory of vertex 5 FPGA

I want to access hardware RAM of FPGA,

 

I want to stote some 8 bit vectors on block ram of vertex FPGA.

I am wondering how to do that .

 

Suppose i write the code for making a RAM :- 

 

 

- - - - - - - - -     - --

 

type ram_type is array (30 downto 0) of std_logic_vector (7 downto 0);
signal RAM: ram_type;

begin

process (ADDR,data,iombar,wrbar,rdbar)
variable sta: std_logic_vector( 2 downto 0);
begin
RAM(0)<="00111110";
RAM(1)<="00001011";
RAM(2)<="00110010";
RAM(3)<="01000000";
RAM(4)<="00000000";
RAM(5)<="00100001";
RAM(6)<="01000000";
RAM(7)<="00000000";
RAM(8)<="01000110";

------- --- --

-- ---- ---- ---

 

so does the values will automatically stored in hardware RAM of FPGA.?

 

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2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
9,231 Views
Registered: ‎08-01-2008

--you can use below example
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rams_21b is
port (CLK : in std_logic;
EN : in std_logic;
ADDR : in std_logic_vector(5 downto 0);
DATA &colon; out std_logic_vector(19 downto 0));
end rams_21b;

architecture syn of rams_21b is
type rom_type is array (63 downto 0) of std_logic_vector (19 downto 0);
signal ROM : rom_type:= (X"0200A", X"00300", X"08101", X"04000", X"08601", X"0233A",
X"00300", X"08602", X"02310", X"0203B", X"08300", X"04002",
X"08201", X"00500", X"04001", X"02500", X"00340", X"00241",
X"04002", X"08300", X"08201", X"00500", X"08101", X"00602",
X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021",
X"00301", X"00102", X"02222", X"04001", X"00342", X"0232B",
X"00900", X"00302", X"00102", X"04002", X"00900", X"08201",
X"02023", X"00303", X"02433", X"00301", X"04004", X"00301",
X"00102", X"02137", X"02036", X"00301", X"00102", X"02237",
X"04004", X"00304", X"04040", X"02500", X"02500", X"02500",
X"0030D", X"02341", X"08201", X"0400D");

signal rdata &colon; std_logic_vector(19 downto 0);
begin

rdata <= ROM(conv_integer(ADDR));

process (CLK)
begin
if (CLK'event and CLK = '1') then
if (EN = '1') then
DATA <= rdata;
end if;
end if;
end process;

end syn;

Thanks and Regards
Balkrishan
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