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Observer vinod_1987
Observer
7,819 Views
Registered: ‎08-17-2015

Aurora 8b/10b design example

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Hi,

        I'm using Aurora 8b/10b ip core, ISE 14.7, virtex 5 Fpga board.

       I want test the loopback of Aurora 8b/10b IP core (Near end PCS) on single board. (virtex 5 ). I have generated Aurora Ip core using core generator with lane = 1, lane rate 3.125 Gbps, GTRefclk= 156.25 Mhz.

issue is - My virtex 5 board as 100Mhz clock (pin number H17). how to convert on board 100Mhz clk to my design(Aurora) GTrefclk 156.25 Mhz.

 

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Community Manager
Community Manager
14,965 Views
Registered: ‎07-23-2012

Re: Aurora 8b/10b design example

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Please refer to http://www.xilinx.com/products/boards/ml505/ml505_10.1_3_1/docs/ml505_aurora.pdf
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Community Manager
Community Manager
14,966 Views
Registered: ‎07-23-2012

Re: Aurora 8b/10b design example

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Please refer to http://www.xilinx.com/products/boards/ml505/ml505_10.1_3_1/docs/ml505_aurora.pdf
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Xilinx Employee
Xilinx Employee
7,806 Views
Registered: ‎08-01-2008

Re: Aurora 8b/10b design example

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Check this XAPP targeting for KC705 board it may help

http://www.xilinx.com/support/documentation/application_notes/xapp1193-aurora-8b10b-on-kc705.pdf

For clocking you need to use PLL . Check the Aurora product guide for detail

Thanks and Regards
Balkrishan
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Observer vinod_1987
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Registered: ‎08-17-2015

Re: Aurora 8b/10b design example

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thank you Smarell.

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