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Adventurer
Adventurer
10,777 Views
Registered: ‎09-27-2010

Aurora 8b10b link downs, Artix

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Hello.

There is 2 Artix FPGAs (xc7a200t-fbg676) on my PCIe device connected by aurora interface.

This Aurora is regulary goes  down  in some PCIe slots and in other PCIe slots it doesn't goes up.
Just before link down I see burst of consequent SoftErrors followed by HardError.

If I set near end PMA loopback link is stable.

Due to this weird dependence on PCIe slot I've decided that there's something wrong with clocks because the reference clocks for Auroras are dirived from PCIe reference clock (100MHz) from PCIe slot with ICS854104 buffer.

Then I've found that PLL0REFCLKLOST = 1.

Now I can't find why...

I've checked that Reference clocks are presented on vias under FPGA (after AC coupling capacitors).

I use MGTREFCLK1P/N dif pair. (AA11, AB11 pins)

in my ucf I've located them:

NET "GTPQ0_P" LOC = AA11;
NET "GTPQ0_N" LOC = AB11;

GT_REFCLK from IBUFDS_GTE2 goes to GTPE2_COMMON/GTREFCLK1

PLL0REFCLKSEL =>"010"

Moreover, I see that

PLL0LOCK=1 (somehow)

and TxOutClkLock of GTPE2_CHANNEL= 1

and PLL_NOT_LOCKED of aurora_8b10b_v8_3_CLOCK_MODULE is 0.

 

How it can be that PLL is locked during the absence of GTREFCLK, and how it can be that there is PLL0REFCLKLOST = 1 if I see this clock on vias near FPGA's pin on both devices wich behaves equally?

 

 

Ilya
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1 Solution

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Moderator
Moderator
19,518 Views
Registered: ‎02-16-2010
Looks like you are using v8.3, this version of the IP does not have some GT related updates required. Please check if you can use the IP from 2014.3 (or) later.
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6 Replies
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Adventurer
Adventurer
10,776 Views
Registered: ‎09-27-2010

If it can help:

constant PLL0_FBDIV_IN      :   integer := 5;
constant PLL0_FBDIV_45_IN   :   integer := 5;
constant PLL0_REFCLK_DIV_IN :   integer := 1;

which means that PLL works on 100MHz * 5 * 5 = 2500 MHz

Ilya
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Adventurer
Adventurer
10,774 Views
Registered: ‎09-27-2010

Single-ended voltage swing of MGTREFCLKN on the via Vpp=500mV .

Ilya
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Adventurer
Adventurer
10,734 Views
Registered: ‎09-27-2010

I've deleted AC coupling capacitors from MGTREFCLK to see if there any changes if there is realy no reference clocks.

Now all LOCK signals are 0 and PLL_NOT_LOCKED of aurora_8b10b_v8_3_CLOCK_MODULE = 1.

I't means that MGTREFCLK existed.

Why PLL0REFCLKLOST was = 1?

Ilya
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Highlighted
Moderator
Moderator
10,703 Views
Registered: ‎02-16-2010
Which version of the IP are you using? Confirm that you are following reset sequence as described in PG046
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
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Highlighted
Moderator
Moderator
19,519 Views
Registered: ‎02-16-2010
Looks like you are using v8.3, this version of the IP does not have some GT related updates required. Please check if you can use the IP from 2014.3 (or) later.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

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Adventurer
Adventurer
10,686 Views
Registered: ‎09-27-2010

It's v8.3.

Thank you very much!

Ilya
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