10-08-2010 05:19 AM
I generated a BRAM using coregen and instanciated it 4 times in my design. In the VHDL file I changed the generic c_init_file_name and gaved different .mif fiel to each blockram instantiated. This works great in simulation. My Ram's are all with the correct data initialised.
The problem is Synthesis: I read the I need to gave .coe file, I already generated them but when i change the above mentioned generic "c_init_file_name" to the .coe file i still got the following warning in synthesis
WARNING:XST:616 - Invalid poperty "init_file_name file.mif or coe": Did not attach to data_ram_4.
Can you tell me how to initialise multiple instances with different coe or mif files for synthesis
Thanks in advance
10-08-2010 11:38 AM
I think the c_init_file attribute is only used in simulation. If you want to initialize 4 different BRAM with different values using coregen, you need to make 4 different cores.
In your case, I would either use the BRAM "INIT_XX" attributes, or infer the BlockRAM and use different functions to initialize each BlockRAM. I use Synplify to do the latter. I'm not sure if XST will do it.
10-10-2010 11:19 PM
first thanks for your response. But does that mean that during creation of the BRAM with coregen the initialisation data is put into the Netlist (.ngc)? Because I already tried that but the size of the netlist hasn't changed.
What do you mean with "INIT_XX" attributes?
Thanks in advance
10-11-2010 06:23 PM
I'm familiar with two ways of doing that:
(1) regenerate the core 4 times, each time using different .coe, and the output is a different netlist.
That can be done from a script: "$ coregen -d -r -p . -b your_core.xco". Inside .xco specify the correct .coe
(2) Initialize BRAMs using data2mem utility, which lets you insert any BRAM data into a bitstream.
10-14-2010 01:04 AM
thanks for our responses it helped me a lot.
I didn't saw a difference in the netlist when i created them with different coe files.
But I found anthoer solution, in the userguide of XST UG621. There are descriptions of how to implement bram only in a vhd file (no coregen required). This kind of vhd brams can bi initilised in simulation and it works also in physical implementation.
In the document are several examples.
So no coregen required (I didn't liked it anyway) :smileyhappy: