We have a design where differential clock goes from pads -> IODELAY -> BUFIO -> bunch of ISERDES_NODELAY. Total fanout of that BUFIO is 32.
1. floorplanner does not show ISERDES_NODELAY so I can't see routing between BUFIO and ISERDES_NODELAY
2. fpga_editor does show ISERDES_NODELAY but does not show BUFIO at all, so we can't see routing from BUFIO to the ISERDES_NODELAYs
3. BUFIO shows variation of about 600ps between min and max cases. This variation is a lot bigger than the variation in the data so it kind of kills our timing. We are shooting to have data valid window of about 600ps in the UCF constraint but we're no where near that.
4. Why does the tool use min clock with max data, and max clock with min data? Is this to deal with on chip variation? These things are in the same IOB I would expect that both data and clock would be of similar process corner?