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Newbie psilos69
Newbie
1,743 Views
Registered: ‎04-27-2010

Big Net Delay inside the CARRY4 circuit of a virtex-5 slice

Hello

I am trying to build a 32-bit adder on a virtex-5 fpga. I need to have access to the carry-outs

of all the stages of the carry look-ahead circuit. In order to do that I used the unisim library

in order to instantiate the CARRY4 Fast Carry Logic Component. This component is used by the ise

during the synthesis of a normal adder in order to form the carry lookahead circuit. Although I

have successfully synthesized the adder using the CARRY4 circuit together with a number of luts

working as xor gates for the sum the delay of my adder is significally bigger comparing to the

delay of the default adder created by the ise. I give you the synthesis reports before place and

route for the two adders.

First is the report from the default adder created by the ise after synthesized a typical

(a+b=c) expression and after is the one I created using the CARRY4 circuit.

Timing constraint: Default path analysis
  Total number of paths / destination ports: 1552 / 32
-------------------------------------------------------------------------
Delay:               4.883ns (Levels of Logic = 35)
  Source:            a<0> (PAD)
  Destination:       d<31> (PAD)

  Data Path: a<0> to d<31>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.694   0.436  a_0_IBUF (a_0_IBUF)
     LUT2:I0->O            2   0.086   0.000  Madd_d_lut<0> (Madd_d_lut<0>)
     MUXCY:S->O            1   0.305   0.000  Madd_d_cy<0> (Madd_d_cy<0>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<1> (Madd_d_cy<1>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<2> (Madd_d_cy<2>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<3> (Madd_d_cy<3>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<4> (Madd_d_cy<4>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<5> (Madd_d_cy<5>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<6> (Madd_d_cy<6>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<7> (Madd_d_cy<7>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<8> (Madd_d_cy<8>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<9> (Madd_d_cy<9>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<10> (Madd_d_cy<10>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<11> (Madd_d_cy<11>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<12> (Madd_d_cy<12>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<13> (Madd_d_cy<13>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<14> (Madd_d_cy<14>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<15> (Madd_d_cy<15>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<16> (Madd_d_cy<16>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<17> (Madd_d_cy<17>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<18> (Madd_d_cy<18>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<19> (Madd_d_cy<19>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<20> (Madd_d_cy<20>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<21> (Madd_d_cy<21>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<22> (Madd_d_cy<22>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<23> (Madd_d_cy<23>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<24> (Madd_d_cy<24>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<25> (Madd_d_cy<25>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<26> (Madd_d_cy<26>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<27> (Madd_d_cy<27>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<28> (Madd_d_cy<28>)
     MUXCY:CI->O           1   0.023   0.000  Madd_d_cy<29> (Madd_d_cy<29>)
     MUXCY:CI->O           0   0.023   0.000  Madd_d_cy<30> (Madd_d_cy<30>)
     XORCY:CI->O           1   0.300   0.235  Madd_d_xor<31> (d_31_OBUF)
     OBUF:I->O                 2.144          d_31_OBUF (d<31>)
    ----------------------------------------
    Total                      4.883ns (4.211ns logic, 0.671ns route)
                                       (86.2% logic, 13.8% route)

Timing constraint: Default path analysis
  Total number of paths / destination ports: 3424 / 64
-------------------------------------------------------------------------
Delay:               6.620ns (Levels of Logic = 11)
  Source:            b<3> (PAD)
  Destination:       c<31> (PAD)

  Data Path: b<3> to c<31>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.694   0.436  b_3_IBUF (b_3_IBUF)
     LUT2:I0->O            1   0.086   0.235  Mxor_xor_out<3>_Result1 (xor_out<3>)
     CARRY4:S3->CO3        2   0.330   0.239  m1 (d_3_OBUF)
     CARRY4:CI->CO3        2   0.091   0.239  m2 (d_7_OBUF)
     CARRY4:CI->CO3        2   0.091   0.239  m3 (d_11_OBUF)
     CARRY4:CI->CO3        2   0.091   0.239  m4 (d_15_OBUF)
     CARRY4:CI->CO3        2   0.091   0.239  m5 (d_19_OBUF)
     CARRY4:CI->CO3        2   0.091   0.239  m6 (d_23_OBUF)
     CARRY4:CI->CO3        2   0.091   0.239  m7 (d_27_OBUF)
     CARRY4:CI->O3         1   0.242   0.235  m8 (c_31_OBUF)
     OBUF:I->O                 2.144          c_31_OBUF (c<31>)
    ----------------------------------------
    Total                      6.620ns (4.042ns logic, 2.577ns route)
                                       (61.1% logic, 38.9% route)


As you can see there is difference of 1.737 ns between the delays of the two adders. This

difference is due to the existance of Net Delays inside the CARRY4 and LUT2 components of my

adder...

Both adders use exactly the same amount of circuit inside the fpga, 8 slices, 32 luts and my

adder has 32 more out ports in order to have the carry-outs of the carry circuit.

There is a direct correspondence between the components used by the two adders and this is

proved by the gate delay which is almost the same, for example a CARRY4 circuit consists of 4

MUXCYs so 4 x 0.023 = 0.092 ns, almost the same with the 0.091 ns of the CARRY4 component I use.

My problem is that I cannot ficure out why there is such a big Net Delay inside the instantiated

circuits... bigger than the Gate Delay itself!

The synthesis was carried out with the default options of the tool.

Do you guys have any idea what is going on?

Thanks in advance!
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