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code_slave
Explorer
Explorer
5,181 Views
Registered: ‎01-04-2009

Boolean optimisation

Would there be any advantage between using either of  the following two terms as regards optimisation?

 

o <= z xor (x and (y xor z))

 

o <=(x and y)xor ((not x) and z)

 

 

 

CS

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4 Replies
rcingham
Teacher
Teacher
5,172 Views
Registered: ‎09-09-2010

What FPGA family?
What version of tools?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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eilert
Teacher
Teacher
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Registered: ‎08-14-2007

Hi,

since you only have three inputs, everything should collapse into one LUT.

 

The smallest LUTs (physically) in Xilinx FPGAs have 4 inputs.

Actual Xilinx FPGA Families have 6-input LUTs.

 

So, when you synthesize these code lines and take a look at the Technology Schematic

there should be LUT3 symbols and the number behind these should be the same, if the two lines are truly equivalent expressions.

e.g. LUT3_B1 <- this hexadecimal number is derived from the truth table of the LUT

 

Have a nice synthesis

  Eilert

 

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bassman59
Historian
Historian
5,164 Views
Registered: ‎02-25-2008


@code_slave wrote:

Would there be any advantage between using either of  the following two terms as regards optimisation?

 

o <= z xor (x and (y xor z))

 

o <=(x and y)xor ((not x) and z)


Write code that makes sense to a human who has to read it, and let the tools optimize it.

----------------------------Yes, I do this for a living.
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code_slave
Explorer
Explorer
5,155 Views
Registered: ‎01-04-2009

Sorry the first  question was trashed due to login timeout

 

FPGA XUPV5-LX110T

tool ISE 14.2

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