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Observer
Observer
8,110 Views
Registered: ‎03-12-2009

CRC64 Virtex5 macro exists on Virtex6?

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Hi

 

I have a design that uses the CRC64 hard macro on a Virtex 5

Does it exist for a Virtex 6?

 

Thanks

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Scholar
Scholar
10,346 Views
Registered: ‎02-27-2008

c,

 

I mean to describe the function you wish in verilog, or VHL, and add it to your design.

 

I suppose you could also do this in c code, using a soft or hard processor, but that might be too slow for your application, and take up more logic, and potentially a number of BRAMs (depending on the length of the packet).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Scholar
Scholar
8,103 Views
Registered: ‎02-27-2008

c,

 

Yes.

 

http://www.xilinx.com/support/documentation/user_guides/ug360.pdf

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Scholar
Scholar
8,097 Views
Registered: ‎02-27-2008

c,


Sorry, I misundersstood, I was thinking of the CRC for the configuration memory.

 

 

 

No, CRC is removed from the MGT's in V6; however you can do this in the fabric if needed.


 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer
Observer
8,092 Views
Registered: ‎03-12-2009

Hi Austin

 

When you say do it in fabric is do it in code?

 

Thanks

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Scholar
Scholar
10,347 Views
Registered: ‎02-27-2008

c,

 

I mean to describe the function you wish in verilog, or VHL, and add it to your design.

 

I suppose you could also do this in c code, using a soft or hard processor, but that might be too slow for your application, and take up more logic, and potentially a number of BRAMs (depending on the length of the packet).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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Observer
Observer
8,084 Views
Registered: ‎03-12-2009

Ok Austin.

 

I have one in VHDL.

 

Thanks

 

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Visitor
Visitor
7,849 Views
Registered: ‎04-22-2010

Hi chico_laranja ,

    If you do not mind, then could you please share that piece of code which dose the same functionality as CRC64 macro? I have a design which was implemented in virtex5 and now it needs to be on virtex6, and i need this code.

 

Thanks,

Sibajit

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Visitor
Visitor
7,848 Views
Registered: ‎04-22-2010

Hi Austin,

        I have a design which was working on virtex5 earlier, and now needs to bo on virtex6.

    As virtex6 does not have CRC64 macro any more, could you please share the code (Verilog/VHDL) which does the same functions as CRC64?

Your help would be highly appriciated!

 

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Observer
Observer
7,828 Views
Registered: ‎03-12-2009

sibpatna

 

You can use the CRC generators online like Outputlogic.com or easics.be

 

Because you are using a Virtex6 you shouldn't have timing problems.

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Visitor
Visitor
7,811 Views
Registered: ‎04-22-2010

Hi chico_laranja,

     Thanks for your response. I have generated few crc codes online, but those codes donot fit in to the same structure of CRC64 macro from Xilinx.

The xilinx macro has below ports:

 

`define POLYNOMIAL 32'h04C11DB7 // 00000100 11000001 00011101 10110111

module CRC64core (
       RESET,
       CRCOUT,
       CRCCLK,
       CRCDATAVALID,
       CRCDATAWIDTH,
       CRCIN,
       CRCRESET
       );
  
   parameter CRC_INIT = 32'hFFFFFFFF;

 

It takes care of CRCDATAWIDTH aswell, but the codes that i got online donot support this data width (here the data width means the byte valid signal of 3 bits). As i have many wrapper files on top of this macro, it would be good if i can get an exact replica of CRC64 macro from xilinx.

 

Thanks,

Sibpatna

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Observer
Observer
3,049 Views
Registered: ‎03-12-2009

sibpatna

 

You need to generate 8 CRC's and make something like a mux.

 

create a CRC32 for 64, 56, 48, 32, 24, 16 and 8 input bits.

Then you mux the results acording to the datawidth.

 

Be careful because xilinx aligns data always to the bit 63 and when you generate CRC of 56 bits input, you have a 55 downto 0 input.

 

It gives some work do make but you can make a simple block.

 

Take some notes: V5_CRC has 2 cycles latency and generated code has 1.

You will need to simulate it to get the same aligment of data and final result because bytes can be transposed.

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Visitor
Visitor
2,499 Views
Registered: ‎04-14-2011
do you have the code that is same as virtex-5 micro?
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