UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
8,976 Views
Registered: ‎03-14-2012

Can I connect four ISERDES sharing the same differential (LVDS) input ?

I need to develop a project that is an interface of ADC-FPGA on a Virtex-6 .
The ADC will send 3 signals in LVDS:

  • BITLCK.
  • FRAME CLOCK.
  • DATA.

The ADC serializes in a factor of 14, data in single channel and DDR mode.

 

I used ISERDES for deserialization, so I created 2 ISERDES (MASTER - SLAVE) for 7 positive bits (get at rising edge of BITCLOK) and other 2 ISERDES (MASTER-SLAVE) for 7 negative bits (get at falling edge of BITCLOCK).

 

I received DATA signal with IBUFDS_DIFF_OUT because i use this structrure for frame alignment either therefore I need both positive and negative values.

 

Following image shows the circuit configuration:

xilinx.jpg

 

When I implement the design i have got the following error:

 

ERROR:Place:1073 - Placer was unable to create RPM[ILOGIC_SHIFT_RPMS] for the
   component serdes_frame_p/iserdese1_master of type ILOGIC for the following
   reason.
   The reason for this issue:
   The structured logic has to be merged with another RPM which causes a
   placement violation for component serdes_frame_n/iserdese1_master. The
   following components are part of this structure:
ERROR:Place:1073 - Placer was unable to create RPM[ILOGIC_SHIFT_RPMS] for the
   component serdes_frame_n/iserdese1_master of type ILOGIC for the following
   reason.
   The reason for this issue:
   Components in this structured logic have conflicting alignment requirements
   that can not be met. The following are the components that require special
   alignment:
   serdes_frame_n/iserdese1_master
   D_P
   Please note that this logic had to be merged with another aligned  RPM. The
   following components are part of this structure:
ERROR:Place:1073 - Placer was unable to create RPM[ILOGIC_SHIFT_RPMS] for the
   component serdes_frame_p/iserdese1_master of type ILOGIC for the following
   reason.
   The reason for this issue:
   The structured logic has to be merged with another RPM which causes a
   placement violation for component serdes_frame_n/iserdese1_master. The
   following components are part of this structure:
ERROR:Place:1073 - Placer was unable to create RPM[ILOGIC_SHIFT_RPMS] for the
   component serdes_frame_n/iserdese1_master of type ILOGIC for the following
   reason.
   The reason for this issue:
   Components in this structured logic have conflicting alignment requirements
   that can not be met. The following are the components that require special
   alignment:
   serdes_frame_n/iserdese1_master
   D_P
   Please note that this logic had to be merged with another aligned  RPM. The
   following components are part of this structure:
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.


Does this happen due to the I/O Tile configuration, because it uses the differential value positive for both ISERDES working at high edge at the same I/O Tile and can´t connect the negative differential value to both ISERDES working at fall edge in another I/O Tile ?

0 Kudos
6 Replies
Xilinx Employee
Xilinx Employee
8,970 Views
Registered: ‎03-18-2008

Re: Can I connect four ISERDES sharing the same differential (LVDS) input ?

No. This isn't going to work. The IOB has a maximum of 2 SERDES. There is not a way of using a single diff data input to drive 4 serdes
0 Kudos
Scholar austin
Scholar
8,963 Views
Registered: ‎02-27-2008

Re: Can I connect four ISERDES sharing the same differential (LVDS) input ?

u,

 

The differential signal must be converted to a single ended signal:  there are no differential signals on the chip, and all the data appears on that one wire, once it is converted from a differential signal into a single ended signal.


Next mistake, is that the data is DDR (uses the rising edge for bit n, and falling edge for bit n+1).


So, you can not deserialize the data the way you have drawn your diagram (either).

 

Go read about DDR.  Go read about differential signaling.

 

Then go think about what you want to do.  Go find the applications notes on how to do it (right).

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Teacher eteam00
Teacher
8,960 Views
Registered: ‎07-21-2009

Re: Can I connect four ISERDES sharing the same differential (LVDS) input ?

Here is one possible implementation approach for you to consider:

 

  • 7x (DDR) BITLCLOCK clock is not used
  • The FRAME CLOCK output (from the ADC) is used as both the timebase reference and the word framing reference
  • Output of IODELAY feeds a master/slave ISERDES in 1:7 deserialise SDR configuration
  • PLL_BASE multiplies the FRAME CLOCK by 14, and this is the serial rate (SDR) clock
  • Bitslip logic is used to word frame all data inputs and the 1:7 FRAME output from ISERDES until the FRAME 1:7 output is 7'b000 0000 and 7'b111 1111.  When the FRAME 1:7 output is properly framed, all of the data inputs should also be properly framed (to 1:7 words).  The FRAME ISERDES output can also be used as a clock enable or mux select for the final 1:2 de-muxing of the data words.

 

Here is a similar discussion from the Spartan-6 forum, which might be translated and applied to your Virtex-6 design.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
8,920 Views
Registered: ‎03-14-2012

Re: Can I connect four ISERDES sharing the same differential (LVDS) input ?

Thanks, I used XAPP866 for my design and it uses diff data input on frame clock alignment. Now I understand that IBUFDS_LVDS_DIFFOUT is used because of IOB configuration, to connect the inputs with two iserdes working at master mode each one, sharing the same input. If am I wrong, please correct me.

0 Kudos
8,912 Views
Registered: ‎03-14-2012

Re: Can I connect four ISERDES sharing the same differential (LVDS) input ?

Thanks Bob for your explanation and your time. I changed a bit the design, now I am using 12-bit configuration instead 14-bit. So I created two 6-bits master iserdes in SDR mode, one working on rising edge of the clock and other working on falling. I followed the configuration on XAPP866 but using the 6 outputs of each iserdes.


Untitled.jpgData uses a very similar configuration.

0 Kudos
Visitor xlsman
Visitor
8,897 Views
Registered: ‎05-12-2011

Re: Can I connect four ISERDES sharing the same differential (LVDS) input ?

Can you give me the XAPP866.zip in the PDF xapp866.pdf?

 

Design Setup
The reference design files are available for download from:
https://secure.xilinx.com/webreg/clickthrough.do?cid=55677
This ZIP file contains:
• Ads527x_V4_V5: Classical implementation of a one-wire interface. Originally developed
for ADS527x ADC devices. [Ref 1]
• Ads6000_V4_1w_NoBramNoProc: A one-wire implementation of an ADS6xxx interface
for a Virtex-4 device.
• Ads6000_V4_2w_NoBramNoProc: A two-wire implementation of an ADS6xxx interface for
a Virtex-4 device.
• Ads_Usb_To_Uart: A sample design to connect the ADC SPI port via a UART_2_USB
device to a PC. This design uses a PicoBlaze processor core.
Both one-wire and two-wire implementations are identical. The two-wire design is preset for
two-wire applications, and the one-wire design is preset for one-wire applications.

 

 

But I find the link is not right ?

 

Please give me the XAPP866.zip which is described in the mail. Thank you very much.

 

E-mail: xuls@ihep.ac.cn

0 Kudos