06-05-2014 03:22 PM
Hi again all,
I am running a Virtex 5 FXT family part and interfacing to some TI ADCs with LVDS DDR outputs. The interface is source synchronous and provides its own clock with the data lines. The clock is connected to a regional clock buffer off of a CC pin. It drives the data inputs and some addiitonal input logic (write side of dual clock FIFOs, etc.).
I am wondering what would happen if everything was running fine and then the clock dropped out for some reason. If it came back, would the IDDR_2CLKs recover and continue passing data, and would the input logic be okay or would we need to reset or reconfigure to get everything right again?
06-05-2014 09:20 PM
06-06-2014 02:47 PM
Assuming your clock is as you described, i.e. the clock pair goes to an IBUFDS and directly to a BUFR or BUFIO, then there's really nothing to reset after a clock loss, and everything should pick up where it left off. If you're actually using some sort of DCM or PLL in the clock path, then that would need to be reset after loss of clock.