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Observer
Observer
9,609 Views
Registered: ‎06-24-2008

Clock dropout, dropped or stopped clock

Hi again all,

I am running a Virtex 5 FXT family part and interfacing to some TI ADCs with LVDS DDR outputs.  The interface is source synchronous and provides its own clock with the data lines.  The clock is connected to a regional clock buffer off of a CC pin.  It drives the data inputs and some addiitonal input logic (write side of dual clock FIFOs, etc.). 

 

I am wondering what would happen if everything was running fine and then the clock dropped out for some reason.  If it came back, would the IDDR_2CLKs recover and continue passing data, and would the input logic be okay or would we need to reset or reconfigure to get everything right again?

 

Thanks,

-Brad

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Community Manager
Community Manager
9,598 Views
Registered: ‎07-23-2012

Hi Brad,

When there is no clock, I believe that the data sent to the IDDR would be lost.

This scenario is similar to de-asserting CE at some point during the operation.

To get a clear understanding on this, I would recommend you to create a small testcase in simulation wherein you either stop the clock or de-assert the CE.

Regards,
Krishna
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Professor
Professor
9,587 Views
Registered: ‎08-14-2007

Assuming your clock is as you described, i.e. the clock pair goes to an IBUFDS and directly to a BUFR or BUFIO, then there's really nothing to reset after a clock loss, and everything should pick up where it left off.  If you're actually using some sort of DCM or PLL in the clock path, then that would need to be reset after loss of clock.

-- Gabor
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