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Visitor
Visitor
10,819 Views
Registered: ‎06-22-2011

Configuring Virtex-6 GTX for PCIe Gen2

I have instantiated a generic GTX Transceiver in a Virtex-6 FPGA.

 

In the design, I control the following GTX ports from the FPGA fabric:

    TXPOSTEMPHASIS_IN

    TXPREEMPHASIS_IN         

    TXDEEMPH_IN

    TXDIFFCTRL_IN

    TXMARGIN_IN

    TXSWING_IN

 

What are the default values for these ports to set the GTX I/O to PCIe gen2 voltage levels?

 

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Explorer
Explorer
10,812 Views
Registered: ‎02-22-2010

Simply generate the core with default values and look into the VHDL (or verilog) <core_name>_gtx.vhd created.

 

        TXDIFFCTRL                           =>      "0000",
       TXPOSTEMPHASIS                 =>      "00000",
        TXPREEMPHASIS                  =>      "0000",
   
 All the other are brought up to the top <core_name>.vhd with no default values. Though if you look into the example design <core_name>_top.vhd all the values are set with zeros.

 

Regards,

Eze

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Moderator
Moderator
10,794 Views
Registered: ‎02-16-2010

you could get these values by generating a GT wrapper using GT wizard from coregen.
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Moderator
Moderator
10,794 Views
Registered: ‎02-16-2010

Use PCIe Gen2 as protocol template...
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