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Observer troelsfr
Observer
11,691 Views
Registered: ‎10-23-2014

Controlling LEDs on Virtex 7

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Hi,

 

I am trying to turn on an LED on by just having a circuit which always has led[0] = 1. I have a constraint file with the line:

 

set_property PACKAGE_PIN AM39 [get_ports {led[0]}]

 

When I run implementation, I get following critical warning:

 

[Common 17-69] Command failed: 'AM39' is not a valid site or package pin name. [/home/tfr/Documents/V707/project_1/project_1.srcs/constrs_1/new/constraints.xdc:15]

 

What is wrong with my constraint file, and how do I access the LED pin of GPIO_LED_0_LS in the correct way?

 

Thanks,

Troels

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1 Solution

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Xilinx Employee
Xilinx Employee
19,593 Views
Registered: ‎01-03-2008

Re: Controlling LEDs on Virtex 7

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A device is define by the part and package. The VC707 uses a 7VX485T-2FFG1761 device, is this what you selected in your project? The AM39 pin is a valid location, so the only reason for the error message is that you are selected a different devic.
------Have you tried typing your question into Google? If not you should before posting.
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9 Replies
Explorer
Explorer
11,681 Views
Registered: ‎02-22-2010

Re: Controlling LEDs on Virtex 7

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Could you specify which device you are using?

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Observer troelsfr
Observer
11,662 Views
Registered: ‎10-23-2014

Re: Controlling LEDs on Virtex 7

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Its Virtex-7 FPGA VC707 Evaluation Kit with a XC7VX485T chip. Is this enough information or do you need some more?

 

 

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Xilinx Employee
Xilinx Employee
19,594 Views
Registered: ‎01-03-2008

Re: Controlling LEDs on Virtex 7

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A device is define by the part and package. The VC707 uses a 7VX485T-2FFG1761 device, is this what you selected in your project? The AM39 pin is a valid location, so the only reason for the error message is that you are selected a different devic.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
Xilinx Employee
Xilinx Employee
11,617 Views
Registered: ‎07-31-2012

Re: Controlling LEDs on Virtex 7

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Hi,

 

For all the valid package pins for each evaluation board you need to check the UCF files. You can check pg 102 of this link - http://www.xilinx.com/support/documentation/boards_and_kits/vc707/ug885_VC707_Eval_Bd.pdf, which shows that AM39 is a valid site.

 

In addition make sure you type this constraint and not copy paste it from another location. Copy pasting can insert unknown characters in the XDC file.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Observer troelsfr
Observer
11,611 Views
Registered: ‎10-23-2014

Re: Controlling LEDs on Virtex 7

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Thanks for your replies.

 

The part is set to "xc7vx485tffg1157-1" and I used the user guide you are refering to, to conclude that AM39 should be a valid site which is why I am confused. However, I am happy to hear that I at least understand the manual correctly :) Note that if I change the port to, for instance, AP15 everything works just fine.

 

My conclusion so far is that it must be my inability to use the graphical user interface. I am pretty sure that the constraints are in the right file (see attached screen shots).

 

 

The synthesis log reads as follows (I've highlighted two (maybe) note worthy things in bold):

 

 

*** Running vivado
    with args -log circuit_top.vds -m64 -mode batch -messageDb vivado.pb -source circuit_top.tcl


****** Vivado v2014.3 (64-bit)
  **** SW Build 1034051 on Fri Oct  3 16:31:15 MDT 2014
  **** IP Build 1028902 on Fri Sep 26 17:35:13 MDT 2014
    ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.

source circuit_top.tcl
# set_param gui.test TreeTableDev
# set_param xicom.use_bs_reader 1
# debug::add_scope template.lib 1
# set_msg_config -id {HDL 9-1061} -limit 100000
# set_msg_config -id {HDL 9-1654} -limit 100000
# set_msg_config -id {Synth 8-256} -limit 10000
# set_msg_config -id {Synth 8-638} -limit 10000
# create_project -in_memory -part xc7vx485tffg1157-1
# set_param project.compositeFile.enableAutoGeneration 0
# set_param synth.vivado.isSynthRun true
# set_property webtalk.parent_dir /home/tfr/Documents/V707/project_1/project_1.cache/wt [current_project]
# set_property parent.project_path /home/tfr/Documents/V707/project_1/project_1.xpr [current_project]
# set_property default_lib xil_defaultlib [current_project]
# set_property target_language Verilog [current_project]
# read_verilog -library xil_defaultlib {
#   /home/tfr/Documents/V707/project_1/project_1.srcs/sources_1/new/circuit1.v
#   /home/tfr/Documents/V707/project_1/project_1.srcs/sources_1/new/circuit_top.v
# }
# read_xdc /home/tfr/Documents/V707/project_1/project_1.srcs/constrs_1/new/constraints.xdc
# set_property used_in_implementation false [get_files /home/tfr/Documents/V707/project_1/project_1.srcs/constrs_1/new/constraints.xdc]
# catch { write_hwdef -file circuit_top.hwdef }
INFO: [Vivado_Tcl 4-279] hardware handoff file cannot be generated as there is no block diagram instance in the design
# synth_design -top circuit_top -part xc7vx485tffg1157-1
Command: synth_design -top circuit_top -part xc7vx485tffg1157-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7vx485t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7vx485t'
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 895.441 ; gain = 142.293 ; free physical = 5653 ; free virtual = 27934
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'circuit_top' [/home/tfr/Documents/V707/project_1/project_1.srcs/sources_1/new/circuit_top.v:23]
INFO: [Synth 8-638] synthesizing module 'circuit1' [/home/tfr/Documents/V707/project_1/project_1.srcs/sources_1/new/circuit1.v:23]
INFO: [Synth 8-256] done synthesizing module 'circuit1' (1#1) [/home/tfr/Documents/V707/project_1/project_1.srcs/sources_1/new/circuit1.v:23]
INFO: [Synth 8-256] done synthesizing module 'circuit_top' (2#1) [/home/tfr/Documents/V707/project_1/project_1.srcs/sources_1/new/circuit_top.v:23]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 930.684 ; gain = 177.535 ; free physical = 5615 ; free virtual = 27897
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 930.684 ; gain = 177.535 ; free physical = 5615 ; free virtual = 27897
---------------------------------------------------------------------------------
Loading clock regions from /opt/Xilinx/Vivado/2014.3/data/parts/xilinx/virtex7/virtex7/xc7vx485t/ClockRegion.xml
Loading clock buffers from /opt/Xilinx/Vivado/2014.3/data/parts/xilinx/virtex7/virtex7/xc7vx485t/ClockBuffers.xml
Loading clock placement rules from /opt/Xilinx/Vivado/2014.3/data/parts/xilinx/virtex7/ClockPlacerRules.xml
Loading package pin functions from /opt/Xilinx/Vivado/2014.3/data/parts/xilinx/virtex7/PinFunctions.xml...
Loading package from /opt/Xilinx/Vivado/2014.3/data/parts/xilinx/virtex7/virtex7/xc7vx485t/ffg1157/Package.xml
Loading io standards from /opt/Xilinx/Vivado/2014.3/data/./parts/xilinx/virtex7/IOStandards.xml
Loading device configuration modes from /opt/Xilinx/Vivado/2014.3/data/parts/xilinx/virtex7/ConfigModes.xml
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/tfr/Documents/V707/project_1/project_1.srcs/constrs_1/new/constraints.xdc]
CRITICAL WARNING: [Common 17-69] Command failed: 'AM39' is not a valid site or package pin name. [/home/tfr/Documents/V707/project_1/project_1.srcs/constrs_1/new/constraints.xdc:15]
Finished Parsing XDC File [/home/tfr/Documents/V707/project_1/project_1.srcs/constrs_1/new/constraints.xdc]
Completed Processing XDC Constraints

INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1287.094 ; gain = 0.000 ; free physical = 5290 ; free virtual = 27571
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1287.094 ; gain = 533.945 ; free physical = 5289 ; free virtual = 27571
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7vx485tffg1157-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1287.094 ; gain = 533.945 ; free physical = 5289 ; free virtual = 27571
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1287.094 ; gain = 533.945 ; free physical = 5289 ; free virtual = 27571
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1287.094 ; gain = 533.945 ; free physical = 5287 ; free virtual = 27568
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics 
---------------------------------------------------------------------------------
Hierarchical RTL Component report 
Module circuit_top 
Detailed RTL Component Info : 
Module circuit1 
Detailed RTL Component Info : 
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 2800 (col length:140)
BRAMs: 2060 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
Start Parallel Synthesis Optimization  : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1287.094 ; gain = 533.945 ; free physical = 5287 ; free virtual = 27568
---------------------------------------------------------------------------------
Start Cross Boundary Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Cross Boundary Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1287.094 ; gain = 533.945 ; free physical = 5287 ; free virtual = 27568
---------------------------------------------------------------------------------
Finished Parallel Reinference  : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1287.094 ; gain = 533.945 ; free physical = 5287 ; free virtual = 27568

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1303.105 ; gain = 549.957 ; free physical = 5271 ; free virtual = 27552
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1303.105 ; gain = 549.957 ; free physical = 5271 ; free virtual = 27552
---------------------------------------------------------------------------------
Finished Parallel Area Optimization  : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1303.105 ; gain = 549.957 ; free physical = 5271 ; free virtual = 27552

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
Finished Parallel Synthesis Optimization  : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1303.105 ; gain = 549.957 ; free physical = 5271 ; free virtual = 27552
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1341.109 ; gain = 587.961 ; free physical = 5234 ; free virtual = 27515
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1341.109 ; gain = 587.961 ; free physical = 5234 ; free virtual = 27515
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1350.121 ; gain = 596.973 ; free physical = 5225 ; free virtual = 27507
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 1350.121 ; gain = 596.973 ; free physical = 5225 ; free virtual = 27506
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 1350.121 ; gain = 596.973 ; free physical = 5225 ; free virtual = 27506
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 1350.121 ; gain = 596.973 ; free physical = 5225 ; free virtual = 27506
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+-----+------+
|      |Cell |Count |
+------+-----+------+
|1     |LUT4 |     1|
|2     |IBUF |     4|
|3     |OBUF |     1|
+------+-----+------+

Report Instance Areas: 
+------+---------+-------+------+
|      |Instance |Module |Cells |
+------+---------+-------+------+
|1     |top      |       |     6|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 1350.121 ; gain = 596.973 ; free physical = 5225 ; free virtual = 27506
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1350.121 ; gain = 149.180 ; free physical = 5225 ; free virtual = 27506
Synthesis Optimization Complete : Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 1350.121 ; gain = 596.973 ; free physical = 5225 ; free virtual = 27506
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Common 17-83] Releasing license: Synthesis
16 Infos, 0 Warnings, 1 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 1364.125 ; gain = 519.680 ; free physical = 5211 ; free virtual = 27492
# write_checkpoint circuit_top.dcp
# catch { report_utilization -file circuit_top_utilization_synth.rpt -pb circuit_top_utilization_synth.pb }
report_utilization: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1364.125 ; gain = 0.000 ; free physical = 5209 ; free virtual = 27490
INFO: [Common 17-206] Exiting Vivado at Mon Dec  1 08:39:51 2014...

 

Screenshot from 2014-12-01 08:28:33.png
Screenshot from 2014-12-01 08:28:36.png
Screenshot from 2014-12-01 08:28:54.png
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Xilinx Employee
Xilinx Employee
11,607 Views
Registered: ‎07-23-2012

Re: Controlling LEDs on Virtex 7

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I was referring to http://www.xilinx.com/support/packagefiles/v7packages/xc7vx485tffg1157pkg.txt and see that there is no AM39 pin in this device.
-----------------------------------------------------------------------------------------------
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Observer troelsfr
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11,606 Views
Registered: ‎10-23-2014

Re: Controlling LEDs on Virtex 7

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It indeed seems that the reason is that I chose the wrong device. I will do some more testing and get back to you.

 

Thanks,

Troels

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Observer troelsfr
Observer
11,596 Views
Registered: ‎10-23-2014

Re: Controlling LEDs on Virtex 7

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So, the problem was that I did not chose a device matching "7VX485T-2FFG1761", but only something matching "7VX485T". Thanks everyone for your help.

Observer troelsfr
Observer
11,590 Views
Registered: ‎10-23-2014

Re: Controlling LEDs on Virtex 7

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Thanks again. I now my "hello world" code up running thanks to your help.

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