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5,964 Views
Registered: ‎11-08-2008

DCM core

Hello All,

I have instantiated a DCM core with an input frequency of 32 MHz clock
signal from the device. I would like to recieve a 96 MHz output signal
from the DCM core, so I set the .xwa file to multiply the incomming
signal by 3. When I generate the bit stream and run the design on my
board, the FX pin doesn't seem to produce a frequency. I know I am
doing something incorrectly here, do I have to reset the DCM core, or
use another signal from the DCM core to obtain my desired output or
whatever ... please help. I have looked at the datasheet and I cannot seem

to resolve this issue.

Thanks,

Tags (3)
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4 Replies
Scholar austin
Scholar
5,958 Views
Registered: ‎02-27-2008

Re: DCM core

u,

 

What tool are you using, ISE, EDK, ??

 

Depending on the template for the instantiation, you will need to connect the reset to a system reset.  If you do not use the reset, and it is tied off (to ground), then if the input glitches whil;e the DCM tries to lock, if will fail to lock.

 

There are other issues if you are adding a DCM module to an EDK project, which involve connecting up all the signals in EDK (port maps, IO connectivity). In ISE, you should be using the primitive from the library, so you get all the syntax, pins, etc. correct.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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5,953 Views
Registered: ‎11-08-2008

Re: DCM core


Hi ,

 

ISE 10.1 (updated) ... :)

 

I used the core generator to produce a dcm that output 96Mhz. I declared the component and instantiated the module, tieing the reset to the system reset and the clock to the master clock, which is 32Mhz.  I used the FX to my FFT core, which was also generated by the core generator. Any other suggestions why it wouldn't produce the desired output frequency ?

 

Thanks

Message Edited by uraniumore235 on 04-15-2010 05:53 PM
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Instructor
Instructor
5,939 Views
Registered: ‎08-14-2007

Re: DCM core

You do need to reset the DCM for at least 3 clock cycles of its input clock after the

input clock is stable.  You should also think about adding logic to reset the DCM if it

loses lock.  Do this by checking the status output of the DCM and adding some

filtering logic to create a reset if lock is lost for some period of time after it has

been asserted.

-- Gabor
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Scholar austin
Scholar
5,935 Views
Registered: ‎02-27-2008

Re: DCM core

u,

 

If you tie the reset to the system reset, be careful, as one of the resets is inverted (I made the same mistake last week).  The signal name isn't obvious, like reset_b so you might think it is high true, but it isn't, as it comes from a pushbutton on the board, which is being pulled up, and when the button is pushed, the signal goes to ground.

 

I added an inversion in the VHDL for that signal, from that pin, and then everything started to work.

 

There is a MicroBlaze reset, the board pushbutton reset (inverted, or low true), and probably others as well (on the XUPV5LX110T pcb with the BSB designs).

 

Other than that, check using FPGA_Editor that the DCM is connected up properly.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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