I am using V4 lx60 FPGA. It is having a clock inputs of 60Mhz and 72 Mhz. The 60 Mhz is used to drive a small portion of the logic inside the FPGA. The majoarity works in 72Mhz. Both clocks are connected to global clock pins. The 72 Mhz clock was given to a DCM and the CLK0 out (72 Mhz) was used. But the 60Mhz was used as such (i.e with out using any DCM) . Then after place and route the clock path delay reported in this clock was around 6ns. So some of output constraints were also not met due to the clock path delay. When a used a DCM for the 60Mhz clock, the problem got solved.
Why is it so ? even if i am not using the DCM the clock will be routed through the dedicated clock paths, right?