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Newbie bantel
Newbie
3,781 Views
Registered: ‎10-17-2011

DDR2_SDRAM VS xps_bram_if_cntlr

I'm a bit confused about following phenomenon.

 

I have two different applications. Both applications include the same function. The first application runs from DDR2_SDRAM and its function is much faster than the function in the application running from xps_bram_if_cntlr. Is that just normal or is something wrong configured. 

 

Thanks for advice 

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2 Replies
Explorer
Explorer
3,774 Views
Registered: ‎08-14-2007

Re: DDR2_SDRAM VS xps_bram_if_cntlr

I've also seen that happen.

 

I asked, but haven't got a really good explanation for it from Xilinx.

 

My theory is that somehow the cache controllers are "nearer" the core than the LMB controller, so if the cache is working well, cached DDR is better than the (as I understand it) zero wait-state LMB...

Martin Thompson
martin.j.thompson@trw.com
http://www.conekt.co.uk/capabilities/electronic-hardware
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Scholar austin
Scholar
3,774 Views
Registered: ‎02-27-2008

Re: DDR2_SDRAM VS xps_bram_if_cntlr

b,

You have not provided enough information to answer your question.

What is the clock frequency of the BRAM? The DDR2_SDRAM? What is the width of the data bus? What is the interface to the memory? Is there a memory controller present?

There may be many reasons why one is faster than the other,
Austin Lesea
Principal Engineer
Xilinx San Jose
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