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Registered: ‎01-08-2011

DVI/HDMI receiver implement on virtex 6 use Rocket IO IP is unstable when TMDS data rate is 250Mbps, 270Mbps or greater is ok

we want implement DVI/HDMI receiver on virtex 6 use rocket for demo. but when TMDS data rate is 250Mbps, (640x480p60 video resolution), the rocket io is not stable.


our hardware is: ML623 fpga board

rocket IO setting: line rate is set 600Mbps, rocket clock is 120Mhz

software is: ISE 12.1


hardware : hdmi source -> hdmi cable -> hdmi connect to SMA board -> ml623 fpga(rocketio + hdmirx soft ip core) -> DAC (VGA out)

hdmi connect to SMA board configure: 8 channel TMDS  line is connect to 3.3V with 50 O resistance . and TMDS line is connect SMA connector use 100nf capacitance.

so my question is:

1. is rocket IO support 250Mbps?

2. is there any other ip core in fpga or from xilinx to support 250Mbps data rate case.  if rocket IO not support 250Mbps,

3. can you suggest some TMDS receiver PHY chip, if not ip core support this.


if xilinx rocket io or ip core support 250Mbps, can you give me example. (the rocket io has main 5 or more configure mode in the user guide. i am puzzle how to select)




my email: 

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