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aobeid
Observer
Observer
5,245 Views
Registered: ‎09-25-2012

Differential Clock Test - How To? - Virtex5 XC5VFX70T

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Hi,

 

I'm currently trying to test the clock synthesizer that is connected to the differential clock pins AB3/AB4 on the Virtex5(XC5VFX70T). I have two test boards, commercial and custom design.

 

Project Brief Description: It includes two processes that simply count up and the corresponding counters are then monitored with ChipScope Generator Workflow.

 

I'm getting the following error while synthesizing my test module in the Mapping step:


ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
single IOB component because the site type selected is not compatible.

.......

Summary:
Symbols involved:
PAD symbol "CLK_P" (Pad Signal = CLK_P)
DIFFAMP symbol "Modul_Test/Modul_IBUFGDS/IBUFDS" (Output Signal =
Modul_Test/CLK_BUF)
Component type involved: IOB
Site Location involved: AB4
Site Type involved: IPAD


 

So, as you can see I'm not able to generate a bitstream for the test. This error is repeated for the other pin AB3.

 

According to the helpful notes by Bob Elkind(), I've taken the following steps before posting:

 

1) Read the relevant parts in Virtex-5 FPGA User Guide - UG190 (v4.5) January 9, 2009 and Virtex-5 Libraries Guide for HDL Designs - ISE 10.1.

2) Searched the Virtex® Family FPGAs forum for similar topics and I've found this Post especially helpful.

3) Didn't post this question on any other forum or on someone else's thread.

4) The project is too simple to be copied from any source.

 

Further more, each clock in the UCF file has the following declaration:


NET "CLK_N" TNM_NET = CLK_N;
TIMESPEC TS_CLK_N = PERIOD "CLK_N" 10 ns HIGH 50%;
NET "CLK_N" LOC=AB3 | DIFF_TERM=true;


 

Interestingly enough, if I comment "NET "CLK_N" LOC=AB3 | DIFF_TERM=true;" the error won't show up for this clock.

 

I'm not sure what or why this error is happening. I've tried the usage example by the aurora_example_design but I've had the same error messages.

 

The question is:

How can I use the differential clocks for a simple test project?

 

 

Note: I've attached the UCF and two VHDL files that makes up the project.

 

Thanks in advance for your help and cooperation.

 

Best Regards

Ahmad Obeid

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1 Solution

Accepted Solutions
aobeid
Observer
Observer
6,529 Views
Registered: ‎09-25-2012

Hi Gabor,

 

Thanks for your reply.

I was looking for a possible design that allows me to test the differential clocks connected to the Virtex5 at AB3/AB4 pins.

As indicated by the posts you referenced, I was able to do a work around that enabled me to do the test.

 

The work around is as follows:


I've used the IP Core Generator to generate an Aurora core which in turn used the differential clocks.

The Aurora Core also outputs TX_OUT_CLK which is buffered using BUFG (Global Clock).

I was able to use the buffered clock output in the simple counter process.


The results from test confirmed my measurements.

 

Best Regards

Ahmad Obeid

 

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2 Replies
gszakacs
Instructor
Instructor
5,230 Views
Registered: ‎08-14-2007

As you can see in the 2nd message of the thread you referenced, it is not possible to use

a MGT reference clock input to directly drive a BUFG.  There may be another way to do this

using some MGT resources, but the bottom line is that you can't connect  "CLK_BUF" directly

to a BUFG.

 

-- Gabor

 

More threads:

 

http://forums.xilinx.com/t5/Connectivity/clocking-questions/m-p/33517

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Need-to-pass-mgt-ref-clk-through-GTP-tile-for-driving-general/m-p/38974

 

-- Gabor
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aobeid
Observer
Observer
6,530 Views
Registered: ‎09-25-2012

Hi Gabor,

 

Thanks for your reply.

I was looking for a possible design that allows me to test the differential clocks connected to the Virtex5 at AB3/AB4 pins.

As indicated by the posts you referenced, I was able to do a work around that enabled me to do the test.

 

The work around is as follows:


I've used the IP Core Generator to generate an Aurora core which in turn used the differential clocks.

The Aurora Core also outputs TX_OUT_CLK which is buffered using BUFG (Global Clock).

I was able to use the buffered clock output in the simple counter process.


The results from test confirmed my measurements.

 

Best Regards

Ahmad Obeid

 

View solution in original post