cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
4,480 Views
Registered: ‎03-22-2010

Differential inputs - width expansion - DIFF_TERM and maximum iserdes rate

Jump to solution

Hi, I have a couple of questions regarding iserdes in virtex 4 and 5, I've spent some hours searching and have no clue:

 

1. When two ISERDES are configured as master-slave to deserialize a data stream with width expansion, the p input is supposed to be connected to the master's D input and the n input to the slave's. However, on doing this, there is no option in the ISERDES to set the IBUFDS DIFF_TERM atribute, so I don't know how to control the presence of the termination resistance. Should I use a IBUFDS primitive even if its single-ended output is unconnected (because it's the two inputs what I'm using for the master-slave ISERDES)?

 

2. In the Virtex 4 Family Overview, when describing the SelectIO specifications, it states: "600 Mb/s HSTL & SSTL (on all single-ended I/O), 1 Gb/s LVDS (on all differential I/O pairs)". However, I can't find in the datasheet-dc&switching characteristics or in the user guide where these limits come from. From the user guide, apparently, the maximum rate in the ISERDES is determined by twice (DDR) the fpga's max input clock => 500 MHz for -12 grade. But I see no reason why single-ended inputs would be slower from the ISERDES point of view. In the datasheet, IOB pad input switching characteristics, there's a list of the different standard's input delays, but I don't see a clear relationship between these numbers and the 600 MB/s in the family overview. Also, in the datasheet, gives 1Gbps for SPI-4.2 in the -11 grade fpga, but the max global clock buffer frequency is 450MHz for this grade, so I can't see how you could use these fpga's to deserialize something faster than 900Mbps. In summary, I'm a little lost regarding ISERDES and max rates at different standards. Can you pleas offer me some guidance here? What happens if I try to deserilize a single-ended input at a rate higher than 600 Mb/s? Do I get corrupted data? How can I know what are the best safe rates for my FPGA (which happens to be -10 grade instead of -12, so I suppose is worse than 600Mbps but I don't know how much).

 

Thanks in advance,

 

Álvaro Navarro

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Explorer
Explorer
5,463 Views
Registered: ‎09-11-2007

1. Your description sounds completely wrong.  Your diff inputs should go to an IBUFDS, which then drives the master ISERDES.  The master and slave are connected throught their SHIFTOUT and SHIFTIN terminals.  I suggest you look at the User's Guide and XAPP855 for guidance.

 

2. The maximum rate at which you can receive serialized data depends on lots of stuff, including jitter and signal integrity.  It's hard to give one number.  I suggest XAPP855 and XAPP707 could be helpful.

 

Barry

View solution in original post

0 Kudos
3 Replies
Highlighted
Explorer
Explorer
5,464 Views
Registered: ‎09-11-2007

1. Your description sounds completely wrong.  Your diff inputs should go to an IBUFDS, which then drives the master ISERDES.  The master and slave are connected throught their SHIFTOUT and SHIFTIN terminals.  I suggest you look at the User's Guide and XAPP855 for guidance.

 

2. The maximum rate at which you can receive serialized data depends on lots of stuff, including jitter and signal integrity.  It's hard to give one number.  I suggest XAPP855 and XAPP707 could be helpful.

 

Barry

View solution in original post

0 Kudos
Highlighted
Observer
Observer
4,466 Views
Registered: ‎03-22-2010

Barry, thanks a lot for your answer.

 

Regarding the width expansion configuration, I was mislead by the paragraph in the user guide saying "If the input is differential, the master ISERDES must be on the positive side of the differential input pair", so I connected each differential terminal to one of the ISERDES's D-inputs (besides connecting the shif terminals), and the thing is that it synthetized, implemented, and worked correctly in the FPGA. But now that I see the drawing that follows that paragraph I see it should be done as you say.

 

I will have a look at those App Notes. From what you say I understand I could actually compile and run a design in which I deserialize single-ended data at 1Gbps, but it won't probably get my data correctly, am I right?

 

Thanks for your time.

Message Edited by alvaro.navarro on 03-22-2010 08:57 AM
0 Kudos
Highlighted
Explorer
Explorer
4,439 Views
Registered: ‎09-11-2007

Regarding deserializing 1Gbps data, you might be successful if you use the alignment techniques in XAPP855.  With a Virtex5 (-2 speed), I am deserializing 800Mbps, and I have a lot of margin.  But I also have fairly short differential trace lengths (< 5 in) and so my data eyes look pretty decent on the scope.

 

Barry

0 Kudos