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Visitor rakesh.kumar
Visitor
3,205 Views
Registered: ‎09-09-2008

ERROR: design is not completely routable for XC6VLX760 FPGA

Hi,

 

I am trying to implement a block of RTL into XC6VLX760 FPGA in multi FPGA system. SERDES are used to communicate among FPGAs. The core clock frequency is 18 MHz. CLK_SERDES is 324 MHz and the CLK_SERDES_2X is 648 MHz for serial data transfer at DDR. The IOs are configured as LVDS pin pairs. 

 

This design gives timing errors and finally design is unroutable. Percentage of number of occupied slices is 92.

 

Synthesis is done using synplify_pro version E201009sp3 and Implementation is done using ISE13.1.

Please see the attached log file for the details.

 

Is it possible to constrain the design so that the ISE tool can route it completely? 

 

How much maximum slice utilization is recommended for the XC6VLX760 FPGA?

 

 

 

 

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2 Replies
Instructor
Instructor
3,188 Views
Registered: ‎08-14-2007

Re: ERROR: design is not completely routable for XC6VLX760 FPGA

Did you notice these warnings in the log file you posted?

 

WARNING:Route:463 - The router has detected a very dense, congested design. It is extremely unlikely the router will be able to finish the
   design and meet your requirements. To prevent excessive run time the router will exit with a partially routed design. This behavior will
   allow you to identify difficult designs earlier. The cause of this behavior is either overly difficult constraints, putting too much
   logic into this device, or an issue with the implementation. If you would prefer a fully routed design, ease the constraints (if any),
   remove some logic from the design, or change the placement before running router again. If you are willing to accept a long run time, set
   the option "-xe c" to override the present behavior.

Updating file: fpga_c_usc0.ncd with current partially routed design.
WARNING:Route:543 - Because this design is experiencing congestion, we recommend you run SmartXplorer with the "Use built-in SmartXplorer
   strategies for Congestion Reduction" radio button enabled in Project Navigator. For command line users, please run SmartXplorer with the
   -cr switch. This will run algorithms designed to avoid logic congestion. For more information on how to run SmartXplorer, please see the
   ISE Help (Project Navigator Users) or the Command Line Tools Users Guide (Command Line Users).

Perhaps setting the "-xe c" command line option and/or running SmartXplorer with the "-cr" switch

would allow you to get farther?

 

-- Gabor

-- Gabor
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Visitor rakesh.kumar
Visitor
3,174 Views
Registered: ‎09-09-2008

Re: ERROR: design is not completely routable for XC6VLX760 FPGA

Thanks Gabor,

 

I tried using -xe c but it is not able to go beyong the par phase 4 even after running for five days. One of our senior team member identified that there is issue with the mapping of multiplier blocks into DSP48E blocks. Due to this the slice utilization has increased to 92%. We are trying to fix it.

 

Regards,

Rakesh

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