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3,886 Views
Registered: ‎08-02-2010

Error: PhysDesignRules:2066 ISERDESE1 conflict

 

I get the following message for in the Bitgen Report when I run 'Generate Programming File':
PhysDesignRules:2066 - Component ISERDESE1_di8 is configured for
   ISERDESE1. A routethru from the /ILOGIC_X1Y129/DDLY to /ILOGIC_X1Y129/O pins,
   configuring a second input path for the DDLY pin is in conflict with
   ISERDESE1 configuration.
I don't use a DDLY, so I'm not sure where this is coming from.  What am I missing, here? Below is my ISERDESE1 instance:
ISERDESE1 #(
      .DATA_RATE("DDR"),           // SDR or DDR
      .DATA_WIDTH(4),              // Parallel data width (2-8, 10)
      .DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (TRUE/FALSE)
      .DYN_CLK_INV_EN("FALSE"),    // Enable DYNCLKINVSEL inversion (TRUE/FALSE)
      // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
      .INIT_Q1(1'b0),
      .INIT_Q2(1'b0),
      .INIT_Q3(1'b0),
      .INIT_Q4(1'b0),
      .INTERFACE_TYPE("NETWORKING"),   // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, or OVERSAMPLE
      .IOBDELAY("NONE"),           // NONE, IBUF, IFD, BOTH
      .NUM_CE(2),                  // Number of clock enables (1 or 2)
      .OFB_USED("FALSE"),          // Select OFB path (TRUE/FALSE)
      .SERDES_MODE("MASTER")      // MASTER or SLAVE
   )
   ISERDESE1_did8 (
      .O(comb_outid[8]),                       // 1-bit Combinatorial output
      // Q1 - Q6: 1-bit (each) Data outputs
      .Q1(di8s[1]),
      .Q2(di8s[3]),
      .Q3(di8s[5]),
      .Q4(di8s[7]),
      .BITSLIP(1'b0),          
      .CE1(1'b1),
      .CE2(1'b1),
      .CLK(clkadci),                   // 1-bit Clock input (fast clock)
      .CLKB(clkadci_not),                 // 1-bit Secondary clock input (fast clock inverse)
      .CLKDIV(g_clk_187_5),             // 1-bit Divided clock input (slow clock)
      .D(did[8]),                       // 1-bit Data input
      .RST(1'b0),                   // 1-bit Active high asynchronous reset input
      // SHIFTIN1/SHIFTIN2: 1-bit (each) Cascade inputs for data width expansion
      .SHIFTIN1(1'b0),
      .SHIFTIN2(1'b0) 
   );

 

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3 Replies
Moderator
Moderator
3,859 Views
Registered: ‎07-30-2007

Re: Error: PhysDesignRules:2066 ISERDESE1 conflict

Where do the clocks and input come from?  The error message makes it sound like the input (from a pin?) is being sent directly into the fabric logic as well as driving the ISERDES.  It might also be trying to input the DDLY signal as well, you should tie the DDLY input to gnd since you are not using it. 

 

-Roy

Roy


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3,843 Views
Registered: ‎08-02-2010

Re: Error: PhysDesignRules:2066 ISERDESE1 conflict

The input comes from differential pin pair, through differential input buffer to become single ended, then into ISERDES. Clock goes through IBUFGDS to MMCM to global clock that drives the ISERDES.   I reduced my design to one bit and attached the project.  It seems that the DDLY is in conflict even when I assign that input to binary 0 value and that the clock is not attaching properly.

 

 

module topmodule(
//fpga outputs and inputs
output [5:0] DACAN, DACAP, 
input XDAC_CLK_N, XDAC_CLK_P, CCLK
);
//internatl signals
wire localClkCounter, clkCounter; 
//clkCounter_not;
//clock for the counter counter
wire [5:0] counterCount;
IBUFGDS #(
      .DIFF_TERM("FALSE"),    // Differential Termination
      .IOSTANDARD("DEFAULT")  // Specify the input I/O standard
   ) IBUFGDS_inst (
      .O(clkCounter),  // Clock buffer output
      .I(XDAC_CLK_P),  // Diff_p clock buffer input (connect directly to top-level port)
      .IB(XDAC_CLK_N) // Diff_n clock buffer input (connect directly to top-level port)
   );
 
  BUFIO BUFIO_inst (
      .O(localClkCounter), // 1-bit output Clock output port (connect to I/O clock loads)
      .I(clkCounter)  // 1-bit input Clock input port (connect to IBUFG)
   );
 //counter 
sixBitCounter dacDummyData (
.clk(localClkCounter),
.q(counterCount)); // Bus [15 : 0] 
//output buffer for bit 0
  OBUFDS #(
      .IOSTANDARD("DEFAULT") // Specify the output I/O standard
   ) OBUFDS_dacaout0 (
      .O(DACAP[0]),     // Diff_p output (connect directly to top-level port)
      .OB(DACAN[0]),   // Diff_n output (connect directly to top-level port)
      .I(counterCount[0])      // Buffer input 
   );
//output buffer for bit 1
  OBUFDS #(
      .IOSTANDARD("DEFAULT") // Specify the output I/O standard
   ) OBUFDS_dacaout1 (
      .O(DACAP[1]),     // Diff_p output (connect directly to top-level port)
      .OB(DACAN[1]),   // Diff_n output (connect directly to top-level port)
      .I(counterCount[1])      // Buffer input 
   );
//output buffer for bit 2
  OBUFDS #(
      .IOSTANDARD("DEFAULT") // Specify the output I/O standard
   ) OBUFDS_dacaout2 (
      .O(DACAP[2]),     // Diff_p output (connect directly to top-level port)
      .OB(DACAN[2]),   // Diff_n output (connect directly to top-level port)
      .I(counterCount[2])      // Buffer input 
   );
//output buffer for bit 3
  OBUFDS #(
      .IOSTANDARD("DEFAULT") // Specify the output I/O standard
   ) OBUFDS_dacaout3 (
      .O(DACAP[3]),     // Diff_p output (connect directly to top-level port)
      .OB(DACAN[3]),   // Diff_n output (connect directly to top-level port)
      .I(counterCount[3])      // Buffer input 
   );
//output buffer for bit 4
  OBUFDS #(
      .IOSTANDARD("DEFAULT") // Specify the output I/O standard
   ) OBUFDS_dacaout4 (
      .O(DACAP[4]),     // Diff_p output (connect directly to top-level port)
      .OB(DACAN[4]),   // Diff_n output (connect directly to top-level port)
      .I(counterCount[4])      // Buffer input 
   );
//output buffer for bit 5
  OBUFDS #(
      .IOSTANDARD("DEFAULT") // Specify the output I/O standard
   ) OBUFDS_dacaout5 (
      .O(DACAP[5]),     // Diff_p output (connect directly to top-level port)
      .OB(DACAN[5]),   // Diff_n output (connect directly to top-level port)
      .I(counterCount[5])      // Buffer input 
   );
endmodule

module topmodule(//fpga outputs to dac inputsoutput [5:0] DACAN, DACAP, input XDAC_CLK_N, XDAC_CLK_P, CCLK);

//internatl signalswire localClkCounter, clkCounter; //clkCounter_not;
//clock for the counter counterwire [5:0] counterCount; IBUFGDS #(      .DIFF_TERM("FALSE"),    // Differential Termination      .IOSTANDARD("DEFAULT")  // Specify the input I/O standard   ) IBUFGDS_inst (      .O(clkCounter),  // Clock buffer output      .I(XDAC_CLK_P),  // Diff_p clock buffer input (connect directly to top-level port)      .IB(XDAC_CLK_N) // Diff_n clock buffer input (connect directly to top-level port)   ); 
  BUFIO BUFIO_inst (      .O(localClkCounter), // 1-bit output Clock output port (connect to I/O clock loads)      .I(clkCounter)  // 1-bit input Clock input port (connect to IBUFG)   );

 //counter sixBitCounter dacDummyData ( .clk(localClkCounter), .q(counterCount)); // Bus [15 : 0] 
//output buffer for bit 0  OBUFDS #(      .IOSTANDARD("DEFAULT") // Specify the output I/O standard   ) OBUFDS_dacaout0 (      .O(DACAP[0]),     // Diff_p output (connect directly to top-level port)      .OB(DACAN[0]),   // Diff_n output (connect directly to top-level port)      .I(counterCount[0])      // Buffer input    ); //output buffer for bit 1  OBUFDS #(      .IOSTANDARD("DEFAULT") // Specify the output I/O standard   ) OBUFDS_dacaout1 (      .O(DACAP[1]),     // Diff_p output (connect directly to top-level port)      .OB(DACAN[1]),   // Diff_n output (connect directly to top-level port)      .I(counterCount[1])      // Buffer input    );

//output buffer for bit 2  OBUFDS #(      .IOSTANDARD("DEFAULT") // Specify the output I/O standard   ) OBUFDS_dacaout2 (      .O(DACAP[2]),     // Diff_p output (connect directly to top-level port)      .OB(DACAN[2]),   // Diff_n output (connect directly to top-level port)      .I(counterCount[2])      // Buffer input    ); //output buffer for bit 3  OBUFDS #(      .IOSTANDARD("DEFAULT") // Specify the output I/O standard   ) OBUFDS_dacaout3 (      .O(DACAP[3]),     // Diff_p output (connect directly to top-level port)      .OB(DACAN[3]),   // Diff_n output (connect directly to top-level port)      .I(counterCount[3])      // Buffer input    ); //output buffer for bit 4  OBUFDS #(      .IOSTANDARD("DEFAULT") // Specify the output I/O standard   ) OBUFDS_dacaout4 (      .O(DACAP[4]),     // Diff_p output (connect directly to top-level port)      .OB(DACAN[4]),   // Diff_n output (connect directly to top-level port)      .I(counterCount[4])      // Buffer input    ); //output buffer for bit 5  OBUFDS #(      .IOSTANDARD("DEFAULT") // Specify the output I/O standard   ) OBUFDS_dacaout5 (      .O(DACAP[5]),     // Diff_p output (connect directly to top-level port)      .OB(DACAN[5]),   // Diff_n output (connect directly to top-level port)      .I(counterCount[5])      // Buffer input    );
endmodule

 

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Newbie ttruong
Newbie
3,607 Views
Registered: ‎05-31-2011

Re: Error: PhysDesignRules:2066 ISERDESE1 conflict

I am experiencing the same error message and wondering if the issue was identified and resolved.  Has anyone else in the Forum seeing this error message?

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