UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor lantiqzhang
Visitor
16,111 Views
Registered: ‎05-29-2013

Error on MMCME2_ADV

Hi,

 

When synthesized Virtex 7 XC7V2000T-FLG1925 by Vivado 2012.4. The following error occured.

 

ERROR: [Drc 23-20] Rule violation (PDRC-34) MMCM_adv_ClkFrequency_div_no_dclk - The computed value 1600.000 (CLKIN1_PERIOD) for the VCO operating frequency of the MMCME2_ADV cell MMCME2_ADV_X1Y11 falls outside the operating range of the MMCM VCO frequency for this device (600 - 1200). Please adjust either the input frequency CLKINx_PERIOD, multiplication factor CLKFBOUT_MULT_F or the division factor DIVCLK_DIVIDE, in order to achieve a VCO frequency within the rated operating range for this device.
ERROR: [Vivado 12-1475] Error(s) found during DRC. NCD file not written.

 

I used the IP generator clocking wizard to create a 5MHz, 10MHz and 20MHz clock output using a 100MHz clock input. The verlog files generated are attached. CLKOUT2 and CLKOUT3 open in my design. Any idea?

 

Regards

 

Liyang

0 Kudos
13 Replies
Guide avrumw
Guide
16,092 Views
Registered: ‎01-23-2009

Re: Error on MMCME2_ADV

The error is in your constraints.

 

The core is correct for what you have asked. You told the core generator that it had a 100MHz input clock and required a 5, 10, and 20MHz output clock.

 

It chose the VCO frequency to be 100 * 32 / 5 = 640MHz, which is in the legal range of 600MHz to 1200MHz.

 

It then set the M0 divider to 128, giving 5MHz, M1 to 64, and M2 to 32, giving 5, 10 and 20MHz respectively.

 

However, your constraints do not match. Based on the error it seems to think the input clock to the MMCM is 250MHz - this is what gives the 250*32/5 = 1600MHz calculation.

 

Presumably you have a "create_clock" command - it should have a period of 10, not a period of 4.

 

Avrum

0 Kudos
Visitor nikita1584
Visitor
15,750 Views
Registered: ‎10-10-2013

Re: Error on MMCME2_ADV

Hello. I have try to "open IP example example design" of 7 series transceivers, then I have added some pin location constrants and generate bitstream.

 

After generating bitstream I have the next error message:

 

[Drc 23-20] Rule violation (PDRC-34) MMCM_adv_ClkFrequency_div_no_dclk - The computed value 500.000 (CLKIN1_PERIOD, net clkin1) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y4 falls outside the operating range of the MMCM VCO frequency for this device (600 - 1600). The computed value is (CLKBFOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input frequency CLKINx_PERIOD (8.000000), multiplication factor CLKFBOUT_MULT_F (4.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

 

Where is coefficient CLKINx_PERIOD (8.000000)?

 

This in instantiation of GTWIZARD_0_CLOCK_MODULE

    GTWIZARD_0_CLOCK_MODULE #
    (
        .MULT                           (4.0),
        .DIVIDE                         (1),
        .CLK_PERIOD                     (6.4),
        .OUT0_DIVIDE                    (5.0),
        .OUT1_DIVIDE                    (1),
        .OUT2_DIVIDE                    (1),
        .OUT3_DIVIDE                    (1)
    )
    txoutclk_mmcm0_i
    (
        .CLK0_OUT                       (gt0_txusrclk_i),
        .CLK1_OUT                       (),
        .CLK2_OUT                       (),
        .CLK3_OUT                       (),
        .CLK_IN                         (gt0_txoutclk_i),
        .MMCM_LOCKED_OUT                (txoutclk_mmcm0_locked_i),
        .MMCM_RESET_IN                  (txoutclk_mmcm0_reset_i)
    );

 And inside of GTWIZARD_0_CLOCK_MODULE we can see:

module GTWIZARD_0_CLOCK_MODULE #
(
    parameter   MULT            =   2,
    parameter   DIVIDE          =   2,
    parameter   CLK_PERIOD      =   6.4,
    parameter   OUT0_DIVIDE     =   2,
    parameter   OUT1_DIVIDE     =   2,
    parameter   OUT2_DIVIDE     =   2,
    parameter   OUT3_DIVIDE     =   2    
)
 (// Clock in ports
  input         CLK_IN,
  // Clock out ports
  output        CLK0_OUT,
  output        CLK1_OUT,
  output        CLK2_OUT,
  output        CLK3_OUT,
  // Status and control signals
  input         MMCM_RESET_IN,
  output        MMCM_LOCKED_OUT
 );

[... some code ...]

  MMCME2_ADV
  #(.BANDWIDTH            ("OPTIMIZED"),
    .CLKOUT4_CASCADE      ("FALSE"),
    .COMPENSATION         ("ZHOLD"),
    .STARTUP_WAIT         ("FALSE"),
    .DIVCLK_DIVIDE        (DIVIDE),
    .CLKFBOUT_MULT_F      (MULT),
    .CLKFBOUT_PHASE       (0.000),
    .CLKFBOUT_USE_FINE_PS ("FALSE"),
    .CLKOUT0_DIVIDE_F     (OUT0_DIVIDE),
    .CLKOUT0_PHASE        (0.000),
    .CLKOUT0_DUTY_CYCLE   (0.500),
    .CLKOUT0_USE_FINE_PS  ("FALSE"),
    .CLKIN1_PERIOD        (CLK_PERIOD),
    .CLKOUT1_DIVIDE       (OUT1_DIVIDE),
    .CLKOUT1_PHASE        (0.000),
    .CLKOUT1_DUTY_CYCLE   (0.500),
    .CLKOUT1_USE_FINE_PS  ("FALSE"),
    .CLKOUT2_DIVIDE       (OUT2_DIVIDE),
    .CLKOUT2_PHASE        (0.000),
    .CLKOUT2_DUTY_CYCLE   (0.500),
    .CLKOUT2_USE_FINE_PS  ("FALSE"),
    .CLKOUT3_DIVIDE       (OUT3_DIVIDE),
    .CLKOUT3_PHASE        (0.000),
    .CLKOUT3_DUTY_CYCLE   (0.500),
    .CLKOUT3_USE_FINE_PS  ("FALSE"),
    .REF_JITTER1          (0.010))
  mmcm_adv_inst
    // Output clocks
   (.CLKFBOUT            (clkfbout),
    .CLKFBOUTB           (clkfboutb_unused),
    .CLKOUT0             (clkout0),
    .CLKOUT0B            (clkout0b_unused),
    .CLKOUT1             (clkout1),
    .CLKOUT1B            (clkout1b_unused),
    .CLKOUT2             (clkout2),
    .CLKOUT2B            (clkout2b_unused),
    .CLKOUT3             (clkout3),
    .CLKOUT3B            (clkout3b_unused),
    .CLKOUT4             (clkout4_unused),
    .CLKOUT5             (clkout5_unused),
    .CLKOUT6             (clkout6_unused),
     // Input clock control
    .CLKFBIN             (clkfbout),
    .CLKIN1              (clkin1),
    .CLKIN2              (1'b0),
     // Tied to always select the primary input clock
    .CLKINSEL            (1'b1),
    // Ports for dynamic reconfiguration
    .DADDR               (7'h0),
    .DCLK                (1'b0),
    .DEN                 (1'b0),
    .DI                  (16'h0),
    .DO                  (do_unused),
    .DRDY                (drdy_unused),
    .DWE                 (1'b0),
    // Ports for dynamic phase shift
    .PSCLK               (1'b0),
    .PSEN                (1'b0),
    .PSINCDEC            (1'b0),
    .PSDONE              (psdone_unused),
    // Other control and status signals
    .LOCKED              (MMCM_LOCKED_OUT),
    .CLKINSTOPPED        (clkinstopped_unused),
    .CLKFBSTOPPED        (clkfbstopped_unused),
    .PWRDWN              (1'b0),
    .RST                 (MMCM_RESET_IN));

[... some code ...]

 I don't understand where Vivado 2013.2 have find CLKINx_PERIOD (8.000000), in above source we can see that in this string

 .CLKIN1_PERIOD        (CLK_PERIOD),

CLK_PERIOD is equal 6.4 regarding with parameter

 

constraint file in attach

 

Thanks!

 

0 Kudos
Moderator
Moderator
15,744 Views
Registered: ‎02-16-2010

Re: Error on MMCME2_ADV

I find the input clock period is overriden in the .xdc file with 8.0 throught the following constraint.
create_clock -name gt0_txusrclk_i -period 8.0 [get_pins -hier -filter {name=~*gt0_gtwizard_0_i*gthe2_i*TXOUTCLK}]

Please correct this as per the design.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
Tags (1)
0 Kudos
Visitor nikita1584
Visitor
15,740 Views
Registered: ‎10-10-2013

Re: Error on MMCME2_ADV

Bitgen Completed Successfully.

 

Thank you!

 

(wizard has generated not correct *.xdc file)

0 Kudos
Visitor embesys
Visitor
12,017 Views
Registered: ‎07-24-2015

Re: Error on MMCME2_ADV

Hello

 

Actually I dont know what is MMCME2_ADV??

 

Does it for any clocking generator??

 

I have  spartan6 xcslx9 tqg144 package. Does it support MMCME2_ADV???

 

If it doesn't then what should I can use in place of it ???

 

0 Kudos
Xilinx Employee
Xilinx Employee
12,014 Views
Registered: ‎02-06-2013

Re: Error on MMCME2_ADV

Hi

 

Spartan6 doesn't have MMCM's

 

Refere below doc for the clocking resources in spartan6 devices.

 

http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos
Visitor embesys
Visitor
12,005 Views
Registered: ‎07-24-2015

Re: Error on MMCME2_ADV

@yenigal

 

Hello 

 

Thanks for your reply..

 

Now I will try by that document...

 

I want to give one input and want to generate one output frequency..

 

Is it possible with that???

0 Kudos
Xilinx Employee
Xilinx Employee
12,003 Views
Registered: ‎02-06-2013

Re: Error on MMCME2_ADV

Hi

 

Yes you can generate output clocks from the input clock.

Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos
Visitor embesys
Visitor
11,988 Views
Registered: ‎07-24-2015

Re: Error on MMCME2_ADV

Thanks

I am trying to implement....

0 Kudos
Visitor embesys
Visitor
8,617 Views
Registered: ‎07-24-2015

Re: Error on MMCME2_ADV

Hello

I am using this chip : Spartan6 XC6SLX9 TQG144..

Is this type of clocking possible???
0 Kudos
Moderator
Moderator
8,577 Views
Registered: ‎02-16-2010

Re: Error on MMCME2_ADV

With Spartan-6 devices you have PLLs to synthesize the clocks. Please use clocking wizard available in coregen tool of ISE to give your input and output frequencies.

This tool provides example design which show how to use PLLs for your design.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Visitor embesys
Visitor
8,556 Views
Registered: ‎07-24-2015

Re: Error on MMCME2_ADV

I am not getting what you want say ....I have given the clock just by .vhd file (code is written in that). And one my question is that my board clk is 50 MHz Can I get 100 MHz from that DCMGEN
0 Kudos
Moderator
Moderator
8,530 Views
Registered: ‎02-16-2010

Re: Error on MMCME2_ADV

yes. you can get 100MHz from 50MHz using DCM.

I was referring to use clocking wizard to generated the example code.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos