05-29-2013 08:01 PM
When synthesized Virtex 7 XC7V2000T-FLG1925 by Vivado 2012.4. The following error occured.
ERROR: [Drc 23-20] Rule violation (PDRC-34) MMCM_adv_ClkFrequency_div_no_dclk - The computed value 1600.000 (CLKIN1_PERIOD) for the VCO operating frequency of the MMCME2_ADV cell MMCME2_ADV_X1Y11 falls outside the operating range of the MMCM VCO frequency for this device (600 - 1200). Please adjust either the input frequency CLKINx_PERIOD, multiplication factor CLKFBOUT_MULT_F or the division factor DIVCLK_DIVIDE, in order to achieve a VCO frequency within the rated operating range for this device.
ERROR: [Vivado 12-1475] Error(s) found during DRC. NCD file not written.
I used the IP generator clocking wizard to create a 5MHz, 10MHz and 20MHz clock output using a 100MHz clock input. The verlog files generated are attached. CLKOUT2 and CLKOUT3 open in my design. Any idea?
05-30-2013 11:55 AM
The error is in your constraints.
The core is correct for what you have asked. You told the core generator that it had a 100MHz input clock and required a 5, 10, and 20MHz output clock.
It chose the VCO frequency to be 100 * 32 / 5 = 640MHz, which is in the legal range of 600MHz to 1200MHz.
It then set the M0 divider to 128, giving 5MHz, M1 to 64, and M2 to 32, giving 5, 10 and 20MHz respectively.
However, your constraints do not match. Based on the error it seems to think the input clock to the MMCM is 250MHz - this is what gives the 250*32/5 = 1600MHz calculation.
Presumably you have a "create_clock" command - it should have a period of 10, not a period of 4.
10-10-2013 02:54 AM
Hello. I have try to "open IP example example design" of 7 series transceivers, then I have added some pin location constrants and generate bitstream.
After generating bitstream I have the next error message:
[Drc 23-20] Rule violation (PDRC-34) MMCM_adv_ClkFrequency_div_no_dclk - The computed value 500.000 (CLKIN1_PERIOD, net clkin1) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y4 falls outside the operating range of the MMCM VCO frequency for this device (600 - 1600). The computed value is (CLKBFOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input frequency CLKINx_PERIOD (8.000000), multiplication factor CLKFBOUT_MULT_F (4.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.
Where is coefficient CLKINx_PERIOD (8.000000)?
This in instantiation of GTWIZARD_0_CLOCK_MODULE
GTWIZARD_0_CLOCK_MODULE # ( .MULT (4.0), .DIVIDE (1), .CLK_PERIOD (6.4), .OUT0_DIVIDE (5.0), .OUT1_DIVIDE (1), .OUT2_DIVIDE (1), .OUT3_DIVIDE (1) ) txoutclk_mmcm0_i ( .CLK0_OUT (gt0_txusrclk_i), .CLK1_OUT (), .CLK2_OUT (), .CLK3_OUT (), .CLK_IN (gt0_txoutclk_i), .MMCM_LOCKED_OUT (txoutclk_mmcm0_locked_i), .MMCM_RESET_IN (txoutclk_mmcm0_reset_i) );
And inside of GTWIZARD_0_CLOCK_MODULE we can see:
module GTWIZARD_0_CLOCK_MODULE # ( parameter MULT = 2, parameter DIVIDE = 2, parameter CLK_PERIOD = 6.4, parameter OUT0_DIVIDE = 2, parameter OUT1_DIVIDE = 2, parameter OUT2_DIVIDE = 2, parameter OUT3_DIVIDE = 2 ) (// Clock in ports input CLK_IN, // Clock out ports output CLK0_OUT, output CLK1_OUT, output CLK2_OUT, output CLK3_OUT, // Status and control signals input MMCM_RESET_IN, output MMCM_LOCKED_OUT ); [... some code ...] MMCME2_ADV #(.BANDWIDTH ("OPTIMIZED"), .CLKOUT4_CASCADE ("FALSE"), .COMPENSATION ("ZHOLD"), .STARTUP_WAIT ("FALSE"), .DIVCLK_DIVIDE (DIVIDE), .CLKFBOUT_MULT_F (MULT), .CLKFBOUT_PHASE (0.000), .CLKFBOUT_USE_FINE_PS ("FALSE"), .CLKOUT0_DIVIDE_F (OUT0_DIVIDE), .CLKOUT0_PHASE (0.000), .CLKOUT0_DUTY_CYCLE (0.500), .CLKOUT0_USE_FINE_PS ("FALSE"), .CLKIN1_PERIOD (CLK_PERIOD), .CLKOUT1_DIVIDE (OUT1_DIVIDE), .CLKOUT1_PHASE (0.000), .CLKOUT1_DUTY_CYCLE (0.500), .CLKOUT1_USE_FINE_PS ("FALSE"), .CLKOUT2_DIVIDE (OUT2_DIVIDE), .CLKOUT2_PHASE (0.000), .CLKOUT2_DUTY_CYCLE (0.500), .CLKOUT2_USE_FINE_PS ("FALSE"), .CLKOUT3_DIVIDE (OUT3_DIVIDE), .CLKOUT3_PHASE (0.000), .CLKOUT3_DUTY_CYCLE (0.500), .CLKOUT3_USE_FINE_PS ("FALSE"), .REF_JITTER1 (0.010)) mmcm_adv_inst // Output clocks (.CLKFBOUT (clkfbout), .CLKFBOUTB (clkfboutb_unused), .CLKOUT0 (clkout0), .CLKOUT0B (clkout0b_unused), .CLKOUT1 (clkout1), .CLKOUT1B (clkout1b_unused), .CLKOUT2 (clkout2), .CLKOUT2B (clkout2b_unused), .CLKOUT3 (clkout3), .CLKOUT3B (clkout3b_unused), .CLKOUT4 (clkout4_unused), .CLKOUT5 (clkout5_unused), .CLKOUT6 (clkout6_unused), // Input clock control .CLKFBIN (clkfbout), .CLKIN1 (clkin1), .CLKIN2 (1'b0), // Tied to always select the primary input clock .CLKINSEL (1'b1), // Ports for dynamic reconfiguration .DADDR (7'h0), .DCLK (1'b0), .DEN (1'b0), .DI (16'h0), .DO (do_unused), .DRDY (drdy_unused), .DWE (1'b0), // Ports for dynamic phase shift .PSCLK (1'b0), .PSEN (1'b0), .PSINCDEC (1'b0), .PSDONE (psdone_unused), // Other control and status signals .LOCKED (MMCM_LOCKED_OUT), .CLKINSTOPPED (clkinstopped_unused), .CLKFBSTOPPED (clkfbstopped_unused), .PWRDWN (1'b0), .RST (MMCM_RESET_IN));
[... some code ...]
I don't understand where Vivado 2013.2 have find CLKINx_PERIOD (8.000000), in above source we can see that in this string
CLK_PERIOD is equal 6.4 regarding with parameter
constraint file in attach
10-10-2013 10:49 PM
07-27-2015 09:13 PM
Actually I dont know what is MMCME2_ADV??
Does it for any clocking generator??
I have spartan6 xcslx9 tqg144 package. Does it support MMCME2_ADV???
If it doesn't then what should I can use in place of it ???
07-27-2015 09:29 PM
Spartan6 doesn't have MMCM's
Refere below doc for the clocking resources in spartan6 devices.
07-27-2015 09:56 PM
07-27-2015 09:59 PM
Yes you can generate output clocks from the input clock.
08-06-2015 04:34 AM
08-06-2015 11:14 PM
08-07-2015 04:24 AM