cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
paulleons
Adventurer
Adventurer
12,554 Views
Registered: ‎01-15-2013

[HDLCompiler 410] Expression has 10 elements ; expected 25

Jump to solution

Hello,

 

I am getting the following error while compiling my VHDL code when I synthesize in PlanAhead but do not get the error with Modelsim. My target device is a Virtex 6 FPGA and using PlanAhead 14.4 to synthesize. 

"

[HDLCompiler 410] Expression has 10 elements ; expected 25 ["C:/Users/pa_leon/Desktop/PEAK_DETECTION/Buffer_implementation/buffer_peak.vhd":71]" .

 

I checked the answer record for this problem and found this link http://www.xilinx.com/support/answers/32975.htm. 

 

I tried to use resize according to the suggestion but it gives me the following error.

[HDLCompiler 841] Expecting type std_logic_vector for <resize>. ["C:/Users/pa_leon/Desktop/PEAK_DETECTION/Buffer_implementation/buffer_peak.vhd":71]

 

I even tried to use to_stdlogic() to convert the RAM block to standard logic(defined already as standard logic) but still i get the same error. 

 

Help would be greatly appreciated. Thank you. 

 

Paul

 

 

 

 

0 Kudos
Reply
1 Solution

Accepted Solutions
vemulad
Xilinx Employee
Xilinx Employee
20,466 Views
Registered: ‎09-20-2012

Hi,

 

Check this thread http://forums.xilinx.com/t5/General-Technical-Discussion/about-the-usage-of-resize-function/td-p/310417

 

You have to change the inputs RAM elements to signed or unsigned, use them in resize function. The result from resize function you need to convert it back to std_logic_vector.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

0 Kudos
Reply
3 Replies
vemulad
Xilinx Employee
Xilinx Employee
20,467 Views
Registered: ‎09-20-2012

Hi,

 

Check this thread http://forums.xilinx.com/t5/General-Technical-Discussion/about-the-usage-of-resize-function/td-p/310417

 

You have to change the inputs RAM elements to signed or unsigned, use them in resize function. The result from resize function you need to convert it back to std_logic_vector.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

0 Kudos
Reply
bassman59
Historian
Historian
12,526 Views
Registered: ‎02-25-2008

Some pro tips:

 

a) Always use (others => '0') when initializing or assigning std_logic_vector and its derivatives to all zero, instead of doing something like foo <= "000000000"; The latter is simply unwieldy and if you change the size of the vector your code breaks.

 

b) The above is doubly true because you use generics to set the width of your vectors. Change the generic in a generic map at a higher level and your code breaks.

 

c) Your RAM won't be implemented as a RAM, since you read from all locations simultaneously when you accumulate.

 

d) There is no reason to keep converting between unsigned and std_logic_vector. Just define the things to be unsigned and be done with it. Especially the counter signal. Get rid of the library use clause for std_logic_unsigned; it's wrong, and als oredundant when you use numeric_std.

 

e) the parallel if state = ... compares should be done with a case statement. In fact, declare an enumerated type for your state register. Oh, did you realize that once your machine gets into the state "10" it's stuck there and never goes anywhere else?

 

f) I'm not sure which statement is causing the "expression has 10 elements" complaint.

 

g) I don't see a call to resize() in your code, but it works on unsigned and signed arguments, not std_logic_vectors. Anyways, your conversion back and forth between unsigned and std_logic_vector is causing problems (it's too confusing to follow) so again, declare average and RAM as unsigned and don't do any type conversions. In fact, I'd declare the signal inp as unsigned. (It is perfectly fine to declare ports as types other than std_logic and std_logic_vector. Really.)

 

 

----------------------------Yes, I do this for a living.
paulleons
Adventurer
Adventurer
12,521 Views
Registered: ‎01-15-2013

Hi,

I thank both of you for your valuable suggestions.

Deepika:
Problem is fixed but I really wonder why modelsim doesn't report those errors???

bassman59:
I am comfortable programming in Verilog but for this project, I am forced to use VHDL.
So type conversion has always been a problem to me.

Regarding pro tips:

a) b) d) - Good suggestions.

c) I understand that it won't use BRAM

e) The code is not complete. I understand that the state do not change after "10".
From my understanding, parallel if statements will be same as a case statement after synthesis (please correct me if I am wrong).

f) & g) I was not sure if ports could be named unsigned. Problem is solved anyway.

Thanks a lot!!!

0 Kudos
Reply