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simong_deleted
Observer
Observer
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Registered: ‎08-26-2009

Has anyone have any luck with the Virtex5 PLL in PMCD mode?

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I’m hitting a problem when using the PLL in PMCD (Phase Matched Clock Divider) mode. It seems that whatever I do the outputs do not toggle.

I tied the RST and the REL inactive (1’b0) just to make sure that these were not the cause.

It all worked in the sim and I did a sanity check and made sure the test output pin actually toggles on the board -all very strange!

 

Here is the instantiation of the PLL_ADV:

 

 

            PLL_ADV #(

                        .BANDWIDTH("OPTIMIZED"),                                         // "HIGH", "LOW" or "OPTIMIZED"

                        .CLKFBOUT_MULT(1),                                                               // Multiplication factor for all output clocks

                        .CLKFBOUT_PHASE(0.0),                                                          // Phase shift (degrees) of all output clocks

                        .CLKIN1_PERIOD(25.000),                                                         // Clock period (ns) of input clock on CLKIN1

                        .CLKIN2_PERIOD(0.000),                                                           // Clock period (ns) of input clock on CLKIN2

                        .CLKOUT0_DIVIDE(8),                                                                // Division factor for CLKOUT0 (1 to 128)

                        .CLKOUT0_DUTY_CYCLE(0.5),                                      // Duty cycle for CLKOUT0 (0.01 to 0.99)

                        .CLKOUT0_PHASE(0.0),                                                            // Phase shift (degrees) for CLKOUT0 (0.0 to 360.0)

                        .CLKOUT1_DIVIDE(4),                                                                // Division factor for CLKOUT1 (1 to 128)

                        .CLKOUT1_DUTY_CYCLE(0.5),                                      // Duty cycle for CLKOUT1 (0.01 to 0.99)

                        .CLKOUT1_PHASE(0.0),                                                            // Phase shift (degrees) for CLKOUT1 (0.0 to 360.0)

                        .CLKOUT2_DIVIDE(2),                                                                // Division factor for CLKOUT2 (1 to 128)

                        .CLKOUT2_DUTY_CYCLE(0.5),                                      // Duty cycle for CLKOUT2 (0.01 to 0.99)

                        .CLKOUT2_PHASE(0.0),                                                            // Phase shift (degrees) for CLKOUT2 (0.0 to 360.0)

                        .CLKOUT3_DIVIDE(1),                                                                // Division factor for CLKOUT3 (1 to 128)

                        .CLKOUT3_DUTY_CYCLE(0.5),                                      // Duty cycle for CLKOUT3 (0.01 to 0.99)

                        .CLKOUT3_PHASE(0.0),                                                            // Phase shift (degrees) for CLKOUT3 (0.0 to 360.0)

                        .CLKOUT4_DIVIDE(1),                                                                // Division factor for CLKOUT4 (1 to 128)

                        .CLKOUT4_DUTY_CYCLE(0.5),                                      // Duty cycle for CLKOUT4 (0.01 to 0.99)

                        .CLKOUT4_PHASE(0.0),                                                            // Phase shift (degrees) for CLKOUT4 (0.0 to 360.0)

                        .CLKOUT5_DIVIDE(1),                                                                // Division factor for CLKOUT5 (1 to 128)

                        .CLKOUT5_DUTY_CYCLE(0.5),                                      // Duty cycle for CLKOUT5 (0.01 to 0.99)

                        .CLKOUT5_PHASE(0.0),                                                            // Phase shift (degrees) for CLKOUT5 (0.0 to 360.0)

                        .COMPENSATION("SYSTEM_SYNCHRONOUS"),           // "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"

                        .DIVCLK_DIVIDE(1),                                                                   // Division factor for all clocks (1 to 52)

                        .EN_REL("FALSE"),                                                                   // Enable release (PMCD mode only)

//                      .EN_REL("TRUE"),                                                                     // Enable release (PMCD mode only)

                        .PLL_PMCD_MODE("TRUE"),                                                     // PMCD Mode, TRUE/FALSE

                        .REF_JITTER(0.100),                                                                  // Input reference jitter (0.000 to 0.999 UI%)

                        .RST_DEASSERT_CLK("CLKIN1")                                  // In PMCD mode, clock to synchronize RST release)

            )

            PLL_ADV_inst (

                        .CLKFBDCM(),                                                                          // Output feedback signal used when PLL feeds a DCM

                        .CLKFBOUT(),                                                                           // General output feedback signal

                        .CLKOUT0(),                                                                                          // One of six general clock output signals

                        .CLKOUT1(incClki),                                                                    // One of six general clock output signals

                        .CLKOUT2(incClk2xi),                                                    // One of six general clock output signals

                        .CLKOUT3(incClkSerDesi),                                             // One of six general clock output signals

                        .CLKOUT4(),                                                                                          // One of six general clock output signals

                        .CLKOUT5(),                                                                                          // One of six general clock output signals

                        .CLKOUTDCM0(),                                                                                  // One of six clock outputs to connect to the DCM

                        .CLKOUTDCM1(),                                                                                  // One of six clock outputs to connect to the DCM

                        .CLKOUTDCM2(),                                                                                  // One of six clock outputs to connect to the DCM

                        .CLKOUTDCM3(),                                                                                  // One of six clock outputs to connect to the DCM

                        .CLKOUTDCM4(),                                                                                  // One of six clock outputs to connect to the DCM

                        .CLKOUTDCM5(),                                                                                  // One of six clock outputs to connect to the DCM

                        .DO(),                                                                                                   // Dynamic reconfig data output (16-bits)

                        .DRDY(),                                                                                               // Dynamic reconfig ready output

                        .LOCKED(),                                                                                           // Active high PLL lock signal

                        .CLKFBIN(incClkIni),                                                      // Clock feedback input

                        .CLKIN1(incClkIni),                                                                     // Primary clock input

                        .CLKIN2(1'b0),                                                                           // Secondary clock input

                        .CLKINSEL(1'b1),                                                                       // Selects 1 = CLKIN1, 0 = CLKIN2

                        .DADDR(5'd0),                                                                           // Dynamic reconfig address input (5-bits)

                        .DCLK(1'b0),                                                                              // Dynamic reconfig clock input

                        .DEN(1'b0),                                                                                            // Dynamic reconfig enable input

                        .DI(16'd0),                                                                                              // Dynamic reconfig data input (16-bits)

                        .DWE(1'b0),                                                                                           // Dynamic reconfig write enable input

                        .REL(1'b0),                    // Clock release input (PMCD mode only)

                        .RST(1'b0)                                                         // Asynchronous PLL reset

//                      .REL(releaseCnt[pReleaseCntW-1]),                    // Clock release input (PMCD mode only)

//                      .RST(~srcClksLocked)                                                   // Asynchronous PLL reset

            );

 

and this is the parameter string that I found back in the fpga editor:

 

BANDWIDTH:OPTIMIZED
CLKFBOUT_DESKEW_ADJUST:0
CLKINSELINV:CLKINSEL
CLKOUT0_DESKEW_ADJUST:0
CLKOUT1_DESKEW_ADJUST:0
CLKOUT2_DESKEW_ADJUST:0
CLKOUT3_DESKEW_ADJUST:0
CLKOUT4_DESKEW_ADJUST:0
CLKOUT5_DESKEW_ADJUST:0
CMT_TEST_CLK_SEL:7
COMPENSATION:EXTERNAL
DIVCLK_DIVIDE:1
EN_REL:FALSE
LOCK_FAST_FILTER:HIGH
LOCK_SLOW_FILTER:HIGH
PLL_2_DCM1_CLK_SEL:6
PLL_2_DCM2_CLK_SEL:6
PLL_AVDD_COMP_SET:3
PLL_AVDD_VBG_PD:1
PLL_AVDD_VBG_SEL:9
PLL_CLK0MX:0
PLL_CLK1MX:0
PLL_CLK2MX:0
PLL_CLK3MX:0
PLL_CLK4MX:0
PLL_CLK5MX:0
PLL_CLKBURST_CNT:0
PLL_CLKBURST_ENABLE:FALSE
PLL_CLKCNTRL:0
PLL_CLKFBMX:0
PLL_CLKFBOUT2_EDGE:TRUE
PLL_CLKFBOUT2_NOCOUNT:TRUE
PLL_CLKFB_MUX_SEL:0
PLL_CLKIN_MUX_SEL:0
PLL_CP_BIAS_TRIP_SHIFT:FALSE
PLL_CP_RES:1
PLL_DIRECT_PATH_CNTRL:FALSE
PLL_DVDD_COMP_SET:3
PLL_DVDD_VBG_PD:1
PLL_DVDD_VBG_SEL:9
PLL_EN:FALSE
PLL_EN_TCLK0:FALSE
PLL_EN_TCLK1:FALSE
PLL_EN_TCLK2:FALSE
PLL_EN_TCLK3:FALSE
PLL_EN_TCLK4:FALSE
PLL_EN_VCO0:TRUE
PLL_EN_VCO1:TRUE
PLL_EN_VCO2:TRUE
PLL_EN_VCO3:TRUE
PLL_EN_VCO4:TRUE
PLL_EN_VCO5:TRUE
PLL_EN_VCO6:TRUE
PLL_EN_VCO7:TRUE
PLL_EN_VCO_DIV1:FALSE
PLL_EN_VCO_DIV6:FALSE
PLL_INC_FLOCK:TRUE
PLL_INC_SLOCK:TRUE
PLL_LF_NEN:3
PLL_LF_PEN:0
PLL_LOCK_CNT:63
PLL_LOCK_CNT_RST_FAST:FALSE
PLL_MAN_LF_EN:FALSE
PLL_NBTI_EN:FALSE
PLL_PFD_CNTRL:8
PLL_PFD_DLY:1
PLL_PMCD_MODE:TRUE
PLL_PWRD_CFG:FALSE
PLL_SEL_SLIPD:FALSE
PLL_SKEW_CNTRL:0
PLL_TCK4_SEL:0
PLL_UNLOCK_CNT:4
PLL_UNLOCK_CNT_RST_FAST:FALSE
PLL_VLFHIGH_DIS:FALSE
RELINV:REL
RESET_ON_LOSS_OF_LOCK:FALSE
RSTINV:RST
RST_DEASSERT_CLK:CLKIN1
WAIT_DCM1_LOCK:FALSE
WAIT_DCM2_LOCK:FALSE

Kind of cryptic! Is there a data sheet which explains these?

 

I'm using ISE 10.1 SP3 on linux.

 

Regards,

++Simon

 

           

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simong_deleted
Observer
Observer
5,707 Views
Registered: ‎08-26-2009

Replying to myself. :-)

 

It seems that I was jumping ahead in instantiating the PLL_ADV and, like the data book says, one should just put in a PMCD component.

I had tried that previously but had hit problems in the mapping stage with an error:

 

ERROR:PhysDesignRules:1520 - Unsupported PLL_ADV configuration. The signal CLKAi
   on the CLKIN1 pin of PLL_ADV comp PMCD_inst is driven by an IOB I pin. The
   CLKFBIN pin signal CLKAi is also driven by an IOB I pin, therefore the
   COMPENSATION attribute must be set EXTERNAL.
ERROR:Pack:1642 - Errors in physical DRC.

 

This happened because I was also driving the 'CLKB' input with the CLKAi signal which I didn't really need.

Thanks to Xilinx tech support for pointing out the data book recommendation as well.

 

Here is the instantiation:

BUFG uuCLKA1_0 (.O(CLKA1), .I(CLKA1i));
BUFG uuCLKA1D2_0 (.O(CLKA1D2), .I(CLKA1D2i));
BUFG uuCLKA1D4_0 (.O(CLKA1D4ck), .I(CLKA1D4i));
//BUFG uuCLKA1D8_0 (.O(CLKA1D8), .I(CLKA1D8i));


// PMCD: Phase-Matched Clock Divider Circuit for Virtex-4

// Xilinx HDL Libraries Guide, version 10.1.2

PMCD #(
    .EN_REL("TRUE"),                        // TRUE/FALSE to allow synchronous deassertion of RST
    .RST_DEASSERT_CLK("CLKA")               // Reset synchronization to which clock: CLKA, CLKB, CLKC or CLKD
)
PMCD_inst (
    .CLKA1(CLKA1i),     // Output CLKA divided by 1
    .CLKA1D2(CLKA1D2i), // Output CLKA divided by 2
    .CLKA1D4(CLKA1D4i), // Output CLKA divided by 4
    .CLKA1D8(),         // Output CLKA divided by 8
    .CLKB1(),           // Output phase matched CLKB
    .CLKC1(),           // Output phase matched CLKC
    .CLKD1(),           // Output phase matched CLKD
    .CLKA(CLKAi),       // Input CLKA
    .CLKB(1'b0),        // Input CLKB
    .CLKC(1'b0),        // Input CLKC
    .CLKD(1'b0),        // Input CLKD
    .REL(rel),          // PCMD release input
    .RST(clkALost)      // Active high reset input
);

// End of PMCD_inst instantiation

 ++Simon

Message Edited by simong on 09-17-2009 08:46 AM

View solution in original post

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simong_deleted
Observer
Observer
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Registered: ‎08-26-2009

Replying to myself. :-)

 

It seems that I was jumping ahead in instantiating the PLL_ADV and, like the data book says, one should just put in a PMCD component.

I had tried that previously but had hit problems in the mapping stage with an error:

 

ERROR:PhysDesignRules:1520 - Unsupported PLL_ADV configuration. The signal CLKAi
   on the CLKIN1 pin of PLL_ADV comp PMCD_inst is driven by an IOB I pin. The
   CLKFBIN pin signal CLKAi is also driven by an IOB I pin, therefore the
   COMPENSATION attribute must be set EXTERNAL.
ERROR:Pack:1642 - Errors in physical DRC.

 

This happened because I was also driving the 'CLKB' input with the CLKAi signal which I didn't really need.

Thanks to Xilinx tech support for pointing out the data book recommendation as well.

 

Here is the instantiation:

BUFG uuCLKA1_0 (.O(CLKA1), .I(CLKA1i));
BUFG uuCLKA1D2_0 (.O(CLKA1D2), .I(CLKA1D2i));
BUFG uuCLKA1D4_0 (.O(CLKA1D4ck), .I(CLKA1D4i));
//BUFG uuCLKA1D8_0 (.O(CLKA1D8), .I(CLKA1D8i));


// PMCD: Phase-Matched Clock Divider Circuit for Virtex-4

// Xilinx HDL Libraries Guide, version 10.1.2

PMCD #(
    .EN_REL("TRUE"),                        // TRUE/FALSE to allow synchronous deassertion of RST
    .RST_DEASSERT_CLK("CLKA")               // Reset synchronization to which clock: CLKA, CLKB, CLKC or CLKD
)
PMCD_inst (
    .CLKA1(CLKA1i),     // Output CLKA divided by 1
    .CLKA1D2(CLKA1D2i), // Output CLKA divided by 2
    .CLKA1D4(CLKA1D4i), // Output CLKA divided by 4
    .CLKA1D8(),         // Output CLKA divided by 8
    .CLKB1(),           // Output phase matched CLKB
    .CLKC1(),           // Output phase matched CLKC
    .CLKD1(),           // Output phase matched CLKD
    .CLKA(CLKAi),       // Input CLKA
    .CLKB(1'b0),        // Input CLKB
    .CLKC(1'b0),        // Input CLKC
    .CLKD(1'b0),        // Input CLKD
    .REL(rel),          // PCMD release input
    .RST(clkALost)      // Active high reset input
);

// End of PMCD_inst instantiation

 ++Simon

Message Edited by simong on 09-17-2009 08:46 AM

View solution in original post

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