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Participant
Participant
7,986 Views
Registered: ‎08-25-2015

Help : virtex 5 MIG Design Creation

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Hello all,

I'm beginner in FPGA control by verilog.

 

I wanna use SRAM DDR2 for writing and reading data.

 

I found ml505_mig_design_creation.pdf 

 

In the guide file, after Generate the MIG(33page), it says I should add overlay files (-ML50x specific UCF file as per

 

AR29313, - Pre-compiled ChipScope Pro design files used to validate the design)

 

Also It says "Modify top level Verilog file" (- Support for ML50x Board as per AR29313, - Add ChipScope Pro to design)

 

I have 2 questions.

 

1. What's the ChipScope ?

 

2. I couldn't find about "AR29313". Is anybody who knows about it?

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Xilinx Employee
Xilinx Employee
15,346 Views
Registered: ‎08-01-2008

Re: Help : virtex 5 MIG Design Creation

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http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/chipscope_pro_sw_cores_ug029.pdf
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
15,347 Views
Registered: ‎08-01-2008

Re: Help : virtex 5 MIG Design Creation

Jump to solution
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/chipscope_pro_sw_cores_ug029.pdf
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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