07-01-2010 12:54 AM
I using Coregen produce a IBERT project , but , I have some control pins,eg: power up pin of external chip...
But i found only a ucf and a ngc files is produced...
so, can i set a pin to high in UCF?
thanks a lot
07-01-2010 01:08 AM
e...I know that I can make a project with "ibert " as a instance, so i can control others pin;
But...also the question, can I set a pin to High in UCF?
07-01-2010 07:04 AM
The UCF file cannot specify acive drive levels of pins, only pullup or pulldown. Even so
if the pin is not included in the project top-level ports, the UCF file does not affect it, only
the bitgen options for unused IOBs. You could use the FPGA editor to drive pins high
or low, but it would probably be easier to build the project including the IBERT than
to go through the pin editing unless it was only one or two pins.
07-02-2010 02:32 PM
Note that there may be another option, e.g. intercepting the output of IBERT, modifying the VHDL, and then rebuilding instead of directly using its bit file output.
http://www.xilinx.com/support/answers/31685.htm (ChipScope Pro IBERT, Virtex-5 FPGA - How can I use a SYSCLK outside the 50-100 MHz range?)
http://www.xilinx.com/support/answers/31684.htm (ChipScope Pro, Virtex-5 IBERT - Can I use the REFCLKOUT as my IBERT system clock? )
I've seen this done in 11.5 to add an output to control something on the board (e.g. mux or oscillator enable) or to change the clock infrastructure appropriately.
You do have to be careful because the batch file has a absolute PC-style path. If you run, this in cygwin shell, you'll get an ngdbuild:604 error as it can't find the IBERT cores because of this. Simply change it appropriately or copy the .bak to a .bat and slightly modify to be a simple script.
I've heard this may not work on 12.1, but haven't tried it though...