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14,525 Views
Registered: ‎02-25-2014

How LUT is configured as Shift register ???

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Hi,

    Can  anyone please explain that How one 6-i/p LUT is configured to 32-bit shif register (SRLC32E) ??

 

 

Thanks in advance.

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Moderator
Moderator
23,171 Views
Registered: ‎01-15-2008

check the following link for the SRL usage from LUT's though this is for 4 input LUT's it can be a good reference for 6 input LUT's

 

http://www.xilinx.com/support/documentation/application_notes/xapp465.pdf

 

--Krishna

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Xilinx Employee
Xilinx Employee
14,524 Views
Registered: ‎08-01-2008

check langauge template

Thanks and Regards
Balkrishan
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Scholar
Scholar
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Registered: ‎06-14-2012

 SRL, This design element is a variable length, 1 to 32 clock cycle shift register implemented within a single look-up

table (LUT).Instantiating the device primitve will implement in LUT only.

 

Library UNISIM;
use UNISIM.vcomponents.all;
-- SRLC32E: 32-bit variable length shift register LUT
-- with clock enable
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.7
SRLC32E_inst : SRLC32E
generic map (
INIT => X"00000000")
port map (
Q => Q, -- SRL data output
Q31 => Q31, -- SRL cascade output pin
A => A, -- 5-bit shift depth select input
CE => CE, -- Clock enable input
CLK => CLK, -- Clock input
D => D -- SRL data input
);
-- End of SRLC32E_inst instantiation

Verilog Instantiation Template
// SRLC32E: 32-bit variable length cascadable shift register LUT
// with clock enable
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.7
SRLC32E #(
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC32E_inst (
.Q(Q), // SRL data output
.Q31(Q31), // SRL cascade output pin
.A(A), // 5-bit shift depth select input
.CE(CE), // Clock enable input
.CLK(CLK), // Clock input
.D(D) // SRL data input
);
// End of SRLC32E_inst instantiation

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Highlighted
14,505 Views
Registered: ‎02-25-2014

Thanks for your reply But Am not asking language template i am aware of all this .

 

My query is related to internal working of 6-i/p LUT as shift register. 

 

If any information  related to that please reply.

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Moderator
Moderator
23,172 Views
Registered: ‎01-15-2008

check the following link for the SRL usage from LUT's though this is for 4 input LUT's it can be a good reference for 6 input LUT's

 

http://www.xilinx.com/support/documentation/application_notes/xapp465.pdf

 

--Krishna

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