04-28-2011 12:16 AM - edited 04-28-2011 12:17 AM
04-28-2011 03:21 AM
the bitfile format is Xilinx company confidential information.
Over the years many attempts have been made to reengineer this with more or less success.
However, with the growing complexity of the chips this task becomes incredibly more complicated over time.
If you want to inspect the correctness of some LUT contents, you can use the fpga-editor (or fpga-edlin, which is scriptable).
Another way would be using chipscope. Connect it to your LUT of choice and check the outputs and inputs.
Will be time consuming to do this for many LUTs.
Besides, do you have doubts that the information from the netlist is not correctly transfered into the bitstream?
If so, why?
Have a nice synthesis
04-28-2011 07:58 AM
I tried to leave some marks on the netlist, by replacing some LUTs' contents with Equivalent logics. Then I can check out the bitfile to see if this bitfile was generated by me. By comparing bitfiles, I can see the change was made, but just don't know if the marks was really made cos I'm not sure what is inside those LUTs actually.
FPGA editor works with ngc file, but can't deal with bitfile. Or if there's any thing can reverse bitfiles to ngc files?
04-28-2011 11:38 PM
did I understand it right that you are trying to put some kind of "watermarks" in the bitfile by manipulating the netlist?
What's the point of this?
A bitfile is a very unique thing, so a simple MD5 would show you wether it's your file or not.
Also what do you mean with "equivalent logic"? Logic is made from LUTs in general. So creating the equivalent logic for some LUT could only be done by spliting up the logic to more than one LUT, thus having impact on the timing of that path.
Yes, the fpga-editor can just visualize netlists, but what more do you need?
Converting a netlist to a bitfile should always create the same result, except for some date/time information bits that may be contained in the bitfile.
So, if you make changes to the netlist, you can check them with the fpga-editor, or you can make the desired changes even simpler from within the fpga-editor.
So what's your idea of the flow?
1) make a design and test it.
2) manipulate the netlist to leave some "marks"
3) create bitfile containing these "marks"
4) configuring FPGA
What are you trying to acheive with these marks, and how?
Have you spent enough thoughts on your concept?
Have a nice synthesis
04-29-2011 03:11 AM
05-03-2011 02:37 AM - edited 05-03-2011 02:41 AM
If you examine the .BIT file with a hex editor, you will see that there is a date+time-stamp near the top. Some of the other parts of the preamble might have interesting fields you could perhaps manipulate.
But the easiest way to check someone's bitfile to see if it was yours would be with a binary file comparison tool, wouldn't it?
06-01-2011 03:47 AM - edited 06-01-2011 03:49 AM
I think I've figured out a way to extract all the LUT's contents, directly read from bitfile, but no configuretion data cos it is not in my sight.
Now I was wondering is it legal to publish my method?