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Explorer
Explorer
10,035 Views
Registered: ‎03-06-2014

How to configure switch boxes in VHDL in Virtex-5 device?

Hello,

 

I am wondering if there is a way to cobfigure switch boxes in VHDL, initialize them and connect them consecutively as you wish? I want to connect a series of switch boex together (the output of first is the input of the next), but I do not know is it possible through VHDL or not?

 

I thank in advance for any kind help and assist.

 

Regards,

@gszakacs

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Scholar
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Registered: ‎02-27-2008

Re: How to configure switch boxes in VHDL in Virtex-5 device?

m,

 

In a word, why?

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
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Registered: ‎03-06-2014

Re: How to configure switch boxes in VHDL in Virtex-5 device?

Thank Austin for your reply. I would like to connect a series of switch boxes consecutively in order to verfiy could it act as a delay line chain? That's why I am looking for a way to do that.

 

Thanks

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Registered: ‎02-27-2008

Re: How to configure switch boxes in VHDL in Virtex-5 device?

m,

 

The carry chain has typically been used in the past to create a programmable fine grained delay line.


Programming interconnect to do that is hard, and results in unpredictable delay, large variation, and a variation in step size.

 

I would not recommend it.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Registered: ‎06-23-2013

Re: How to configure switch boxes in VHDL in Virtex-5 device?

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Explorer
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Registered: ‎03-06-2014

Re: How to configure switch boxes in VHDL in Virtex-5 device?

Dear @dwisehart

 

Hello,

 

I just tumbled again to your post and the hint that you proposed ! Do you know how to configure IODELAY blocks in VHDL and what is the step size of delay in consecutive connected blocks?

 

Thanks and Regards,

 

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Registered: ‎06-23-2013

Re: How to configure switch boxes in VHDL in Virtex-5 device?

@msdarvishi I do not know how to configure IODELAY blocks in VHDL, but the templates in Vivado should help you out.  If not, post a separate question asking for help.

 

As for step size, it depends on the REFCLK you use.  The effects of different frequencies are discussed here: http://www.xilinx.com/support/documentation/application_notes/xapp707.pdf

 

Daniel

 

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