07-09-2015 07:25 AM
I am wondering if there is a way to cobfigure switch boxes in VHDL, initialize them and connect them consecutively as you wish? I want to connect a series of switch boex together (the output of first is the input of the next), but I do not know is it possible through VHDL or not?
I thank in advance for any kind help and assist.
07-09-2015 10:45 AM
Thank Austin for your reply. I would like to connect a series of switch boxes consecutively in order to verfiy could it act as a delay line chain? That's why I am looking for a way to do that.
07-09-2015 11:01 AM - edited 07-09-2015 11:01 AM
The carry chain has typically been used in the past to create a programmable fine grained delay line.
Programming interconnect to do that is hard, and results in unpredictable delay, large variation, and a variation in step size.
I would not recommend it.
07-09-2015 11:42 AM
10-20-2016 10:11 AM
I just tumbled again to your post and the hint that you proposed ! Do you know how to configure IODELAY blocks in VHDL and what is the step size of delay in consecutive connected blocks?
Thanks and Regards,
10-20-2016 01:14 PM
@msdarvishi I do not know how to configure IODELAY blocks in VHDL, but the templates in Vivado should help you out. If not, post a separate question asking for help.
As for step size, it depends on the REFCLK you use. The effects of different frequencies are discussed here: http://www.xilinx.com/support/documentation/application_notes/xapp707.pdf