04-06-2010 04:51 AM
I'm interested on using the DCM ADV cell to generate a clock of programmable frequencies for an application. It should be straighforward yet I haven't manage to control the M and D parameters for the clock.
The Virtex-4 configuration guide just lists the signals to access the dynamic reconfiguration port of the DCM ADV, though the virtex-5 guide does show them in a timing diagram. They don't contradict themselves, just two registers to write on the Virtex-4 (0x50 for M, 0x52 for D) instead of a single one on the virtex-5...even better. Checked out the setup/hold timing of DCLK on the datasheet.
So I wrote a test code and no luck! The signals are programmed to follow the chronogram shown in the virtex5 guide, and the DCM has its reset held meanwhile.
Could someone suggest something please? I'd appreciate
Many thanks in advance,
11-26-2010 07:58 AM
11-26-2010 08:15 AM
Chapter 6 of the Virtex-4 Configuration Guide has good details on how to use the DRP interface.
I've used this many times without any issues. What kind of problem are you having?
11-29-2010 06:29 AM
Thanks for the pointer. I did find ug191 (for my Virtex5 device) and put a state machine together to preload the M and D values before reset is released. My problem is that I don't trust the models....and consequently don't have a lot of faith this will work when I burn it.
The documentation only specifies the addresses for the M & D settings. There is also another for the low and high range. What other registers need to be considered?
11-29-2010 07:38 AM
When you ... "burn" it? You do realize that you can reprogram an FPGA a virtually unlimited number of times, so why don't you simply verify your design in silicon?
Besides, if you don't trust the simulation models of the FPGA primitives, then you should verify that they work correctly. How else are you going to simulate your design without implementing and downloading it to the device every time?