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Voyager
Voyager
9,062 Views
Registered: ‎04-10-2012

How to cross multi-phase clock boundries

I have a clock generator on a custom board that creates multiple copies of a 200MHz signal to drive many components (ADCs/DACs/FPGA/etc).  The FPGA (a V6) then reads the ADC/DAC clocks and using it for clocking in/out signals.  What this means is that I have to cross clock domains (hopefully that is the right verbage here) twice (from ADC to FPGA, from FPGA to DAC).


What I am unsure of, is the proper way to handle the crossings.  The clocks will be running at the same frequency and should have consistent phase offsets (meaning miminal jitter), but I assume that due to trace lengths and paths within the FPGA, they will not be 100% in phase with each other.  The signals will be busses of data (12b and 16b wide).

 

I have been reading about using a FIFO core that has the source clock write in the data and the destination clock used to read the data out.  Is that the best way to handle this?

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Historian
Historian
9,052 Views
Registered: ‎02-25-2008

You didn't say whether the ADC interface is source synchronous or whether it is clocked by the same clock as the FPGA.

----------------------------Yes, I do this for a living.
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Voyager
Voyager
9,049 Views
Registered: ‎04-10-2012

They are all clocked by the same IC that is generating the 200MHz. So everything should be at the same frequency and any skew in rising/falling edges should be consisten (I would assume) once things are powered up and stable.

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