01-20-2016 02:55 PM
I have a very high speed design implemented into Virtex-5 FPGA operating at 500MHz. I am using ISE14.7. The design is fully placed and routed with no errors and warnings ! Also, the post place&route simulation results are great. Now, I am looking a way how to assure that this design works properly in reality while it is implemented into the FPGA??
1. The design is very high speed and no expernal probe can be connected to the pins for measurement.
2. The Virtex-5 pins are not capable to handle that frequency out for measurement since they are too slow.
Any help or hint rovided by you is cordially appreciated :)
01-21-2016 03:12 AM
01-26-2016 10:55 AM
Thanks for your reply. As I know, ChipScope is ONLY for debugging the design and it is not functional at high speeds. You see, my clock signal is very high frequency and very fast. I do not think that ChopScope will be usable !! What is your idea??
01-28-2016 10:10 AM
02-08-2016 01:06 PM
Thanks @venkata for your kind reply. Indeed, I am working with very small delays in my design and the respond of my circuit to those delays are very important. Do you think that ChipScope can trace the delays signals inside FPGA? I mean for example I have signal 1 & signal 2 and 100 ps after, the signal_x that is the XOR of two former signals must be raised. Can I trace the circuit with this accuracy using ChipScope?
02-08-2016 01:09 PM
Another point that I have to mention regarding your point for the maximum operation frequency of Virtex-5, the amount of 710 MHz, may depend on the volume of your circuit that you implement into FPGA, I think ! Indeed, the 710 MHz is usable when you implement a very simple circuit with OBLY 1 LUT or 1 FlipFlop, isn't it?? Please correct my whenever I am going wrong :)
02-08-2016 11:42 PM
yes. the 710 Mhz is for the best case scenario of 1 LUT 1 FF situation. I am actually surprised that you are able meet timing in a general design on Virtex 5 with 500 Mhz clock. It must be a very nicely pipelined design(with a few logic levels between two FF).
Anyway, chip scope core can only probe signal at its input frequency rate. hence , combinational componet delay of 100 ps between signalx and signal1/2 will not be noticeable on chip scope. (You can see the delay in Post implementation timing simulation though).
02-15-2016 02:13 PM
Thanks for your reply. You mentioned a very good point that is :
core can only probe signal at its input frequency rate.
Just as a note to be sure that I understood your point correctly, when I configured ChipScope, I chose the JTAG Clock by right-clicking on Generate Programming File --> Startup Options --> FPGA Startup Clock.
This means that the FPGA is clocked by JTAG Clock. So, If I use a PLL core to multiply this frequency internally, may I trace it with ChipScope??
If you think this method is also infeasible, could you please give a hint how to design a TRACER (TRACKER) circuit using VHDL that is not affecting my original design functionality, but can trace and report the status of each signal at any time that I want?? I have the idea of using BRAMs to register the signals' status but I do not know how to make it temporal??
Kind helps are coardially appreciated.
Thanks and Regards,
02-15-2016 09:16 PM
You can use a PLL and generate a higher frequency to drive the chipscope core and probe the signal of your interest.
But it is defintiely not possible to monitor delay of 100 ps ( which needs probing at more than 10 GHz frequency. As you know, this is impossible).
The use of chipscope core is essential to montor the signal status/signal changes and not to monitor combinational delays between signal changes(as you intend). The only reliable way for you to check the combinational delays between two signals(in order of ps) is doing post-implementation timing simulation.
Note: IN general, it is best practice to give the same clock input to chipscope core as of the signals you are monitoring.( to avoid timing issues)
02-16-2016 07:54 AM
Thanks for your kind reply and nice explanation of what chipscope does.
You know, I did the post-place and route simulation and it is working very well and all timing constraints were met and I could see those combinational delays in the range of picoseconds. But, my teacher asked me that theer is not a guarantee for the design to work in real world on the FPGA as well !!!! which is against what Xilinx does promise for post-place and route accuracy, I think !!
Now, I am looking to find a test bench in order to ensure that my design is working properly in real world as well. Do you have any recommendation anout it??
Thanks and Regards,